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5962-8960901EA Datasheet

  • 5962-8960901EA

  • High-Speed CMOS Logic Phase-Locked Loop with VCO

  • 436.38KB

  • 28頁

  • TI

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CD54HC4046A, CD74HC4046A,
CD54HCT4046A, CD74HCT4046A
Data sheet acquired from Harris Semiconductor
SCHS204J
February 1998 - Revised December 2003
High-Speed CMOS Logic
Phase-Locked Loop with VCO
Description
The 鈥橦C4046A and 鈥橦CT4046A are high-speed silicon-gate
CMOS devices that are pin compatible with the CD4046B of
the 鈥?000B鈥?series. They are specified in compliance with
JEDEC standard number 7.
The 鈥橦C4046A and 鈥橦CT4046A are phase-locked-loop
circuits that contain a linear voltage-controlled oscillator
(VCO) and three different phase comparators (PC1, PC2 and
PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage
signals, or indirectly coupled (with a series capacitor) to small
voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 4046A forms a second-order loop
PLL. The excellent VCO linearity is achieved by the use of
linear op-amp techniques.
Features
[ /Title
(CD74
HC404
6A,
CD74
HCT40
46A)
/Sub-
ject
(High-
Speed
CMOS
鈥?Operating Frequency Range
- Up to 18MHz (Typ) at V
CC
= 5V
- Minimum Center Frequency of 12MHz at V
CC
= 4.5V
鈥?Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
鈥?Excellent VCO Frequency Linearity
鈥?VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
鈥?Minimal Frequency Drift
鈥?Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at VOL, VOH
Ordering Information
PART NUMBER
CD54HC4046AF3A
CD54HCT4046AF3A
CD74HC4046AE
CD74HC4046AM
CD74HC4046AMT
CD74HC4046AM96
CD74HC4046ANSR
CD74HC4046APWR
CD74HC4046APWT
CD74HCT4046AE
CD74HCT4046AM
CD74HCT4046AMT
CD74HCT4046AM96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Applications
鈥?FM Modulation and Demodulation
鈥?Frequency Synthesis and Multiplication
鈥?Frequency Discrimination
鈥?Tone Decoding
鈥?Data Synchronization and Conditioning
鈥?Voltage-to-Frequency Conversion
鈥?Motor-Speed Control
NOTE: When ordering, use the entire part number. The suf鏗亁es 96
and R denote tape and reel. The suf鏗亁 T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
1

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