CD54HC299, CD74HC299,
CD54HCT299, CD74HCT299
Data sheet acquired from Harris Semiconductor
SCHS178C
January 1998 - Revised May 2003
High-Speed CMOS Logic
8-Bit Universal Shift Register; Three-State
Description
The 鈥橦C259 and 鈥橦CT299 are 8-bit shift/storage registers
with three-state bus interface capability. The register has four
synchronous-operating modes controlled by the two select
inputs as shown in the mode select (S0, S1) table. The mode
select, the serial data (DS0, DS7) and the parallel data (I/O
0
- I/O
7
) respond only to the low-to-high transition of the clock
(CP) pulse. S0, S1 and data inputs must be stable one set-
up time prior to the clock positive transition.
The Master Reset (MR) is an asynchronous active low input.
When MR output is low, the register is cleared regardless of
the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the 鏗乺st stage.
The three-state input/output I(/O) port has three modes of
operation:
1. Both output enable (OE1 and OE2) inputs are low and S0
or S1 or both are low, the data in the register is presented
at the eight outputs.
2. When both S0 and S1 are high, I/O terminals are in the
high impedance state but being input ports, ready for par-
allel data to be loaded into eight registers with one clock
transition regardless of the status of OE1 and OE2.
3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.
Features
鈥?Buffered Inputs
[ /Title
(CD74
HC299
,
CD74
HCT29
9)
/Sub-
ject
(High
Speed
CMOS
Logic
8-Bit
Uni-
versal
Shift
鈥?Four Operating Modes: Shift Left, Shift Right, Load
and Store
鈥?Can be Cascaded for N-Bit Word Lengths
鈥?I/O
0
- I/O
7
Bus Drive Capability and Three-State for
Bus Oriented Applications
鈥?Typical f
MAX
= 50MHz at V
CC
= 5V, C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
Pinout
CD54HC299, CD54HCT299
(CERDIP)
CD74HC299, CD74HCT299
(PDIP, SOIC)
TOP VIEW
S0
OE1
OE2
I/O
6
I/O
4
I/O
2
I/O
0
Q0
MR
1
2
3
4
5
6
7
8
9
20 V
CC
19 S1
18 DS7
17 Q7
16 I/O
7
15 I/O
5
14 I/O
3
13 I/O
1
12 CP
11 DS0
Ordering Information
PART NUMBER
CD54HC299F3A
CD54HCT299F3A
CD74HC299E
CD74HC299M
CD74HC299M96
CD74HCT299E
CD74HCT299M
CD74HCT299M96
TEMP. RANGE (
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld CERDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
GND 10
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
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