SN54AC374, SN74AC374
OCTAL D TYPE EDGE TRIGGERED FLIP FLOPS
WITH 3 STATE OUTPUTS
SCAS543E 鈭?OCTOBER 1995 - REVISED OCTOBER 2003
D
D
D
D
D
2-V to 6-V V
CC
Operation
Inputs Accept Voltages to 6 V
Max t
pd
of 9.5 ns at 5 V
3-State Noninverting Outputs Drive Bus
Lines Directly
Full Parallel Access for Loading
SN54AC374 . . . J OR W PACKAGE
SN74AC374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the 鈥橝C374 devices are
D-type edge-triggered flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines in bus-organized systems without need
for interface or pullup components.
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
SN54AC374 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
2D
2Q
3Q
3D
4D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PDIP 鈭?N
SOIC 鈭?DW
鈭?0 C 85擄C
鈭?0擄C to 85 C
SOP 鈭?NS
SSOP 鈭?DB
TSSOP 鈭?PW
CDIP 鈭?J
鈭?5 C 125擄C
鈭?5擄C to 125 C
CFP 鈭?W
LCCC 鈭?FK
PACKAGE鈥?/div>
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AC374N
SN74AC374DW
SN74AC374DWR
SN74AC374NSR
SN74AC374DBR
SN74AC374PW
SN74AC374PWR
SNJ54AC374J
SNJ54AC374W
SNJ54AC374FK
AC374
SNJ54AC374J
SNJ54AC374W
SNJ54AC374FK
AC374
AC374
AC374
TOP-SIDE
MARKING
SN74AC374N
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
4Q
GND
CLK
5Q
5D
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
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