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5962-8685301CA Datasheet

  • 5962-8685301CA

  • Dual D Flip-Flop with Set and Reset Positive-Edge Trigger

  • 276.08KB

  • 12頁

  • TI

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CD54HC74, CD74HC74,
CD54HCT74, CD74HCT74
Data sheet acquired from Harris Semiconductor
SCHS124D
January 1998 - Revised September 2003
Dual D Flip-Flop with Set and Reset
Positive-Edge Trigger
Description
The 鈥橦C74 and 鈥橦CT74 utilize silicon gate CMOS technology
to achieve operating speeds equivalent to LSTTL parts.
They exhibit the low power consumption of standard CMOS
integrated circuits, together with the ability to drive 10 LSTTL
loads.
This 鏗俰p-鏗俹p has independent DATA, SET, RESET and
CLOCK inputs and Q and Q outputs. The logic level present
at the data input is transferred to the output during the
positive-going transition of the clock pulse. SET and RESET
are independent of the clock and are accomplished by a low
level at the appropriate input.
The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
Features
[ /Title
(CD54H
C74,
CD74H
C74,
CD74H
CT74)
/Subject
(Dual D
Flip-
Flop
with Set
鈥?Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
鈥?Asynchronous Set and Reset
鈥?Complementary Outputs
鈥?Buffered Inputs
鈥?Typical f
MAX
= 50MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC74F3A
CD54HCT74F3A
CD74HC74E
CD74HC74M
CD74HC74MT
CD74HC74M96
CD74HCT74E
CD74HCT74M
CD74HCT74MT
CD74HCT74M96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel. The suf鏗亁 T denotes a small-quantity reel of
250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1

5962-8685301CA 產品屬性

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