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5962-8515301CA Datasheet

  • 5962-8515301CA

  • Dual J-K Flip-Flop with Reset Negative-Edge Trigger

  • 13頁(yè)

  • TI

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CD54HC73, CD74HC73,
CD74HCT73
Data sheet acquired from Harris Semiconductor
SCHS134E
February 1998 - Revised September 2003
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
Description
The 鈥橦C73 and CD74HCT73 utilize silicon gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These 鏗俰p-鏗俹ps have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible
with the standard LS logic family.
Features
[ /Title
(CD74
HC73,
CD74
HCT73
)
/Sub-
ject
(Dual
J-K
Flip-
Flop
鈥?Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
鈥?Asynchronous Reset
鈥?Complementary Outputs
鈥?Buffered Inputs
鈥?Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC73F3A
CD74HC73E
CD74HC73M
CD74HC73MT
CD74HC73M96
CD74HCT73E
CD74HCT73M
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel. The suf鏗亁 T denotes a small-quantity reel of
250.
Pinout
CD54HC73 (CERDIP)
CD74HC73, CD74HCT73 (PDIP, SOIC)
TOP VIEW
1CP 1
1R 2
1K 3
V
CC
4
2CP 5
2R 6
2J 7
14 1J
13 1Q
12 1Q
11 GND
10 2K
9 2Q
8 2Q
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1

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