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56F8356 Datasheet

  • 56F8356

  • 56F8356 16-bit Hybrid Controller

  • 160頁(yè)

  • MOTOROLA   MOTOROLA

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Freescale Semiconductor, Inc.
MC56F8356/D
Rev. 6.0, 6/2004
56F8356
Preliminary Technical Data
56F8356 16-bit Hybrid Controller
鈥?Up to 60 MIPS at 60MHz core frequency
鈥?DSP and MCU functionality in a unified,
C-efficient architecture
鈥?Access up to 1MB of off-chip program and data
memory
鈥?Temperature Sensor
鈥?Two Quadrature Decoders
鈥?Optional on-chip regulator
鈥?FlexCAN module
鈥?Two Serial Communication Interfaces (SCIs)
鈥?Up to two Serial Peripheral Interfaces (SPIs)
鈥?Up to four general-purpose Quad Timers
鈥?Computer Operating Properly (COP) / Watchdog
鈥?JTAG/Enhanced On-Chip Emulation (OnCE鈩? for
unobtrusive, real-time debugging
鈥?Up to 62 GPIO lines
鈥?144-pin LQFP Package
Freescale Semiconductor, Inc...
鈥?Chip Select Logic for glueless interface to ROM
and SRAM
鈥?256KB of Program Flash
鈥?4KB of Program RAM
鈥?8KB of Data Flash
鈥?16KB of Data RAM
鈥?16KB of Boot Flash
鈥?Two 6-channel PWM modules
鈥?Four 4-channel, 12-bit ADCs
RSTO
EMI_MODE
EXTBOOT
5
V
PP
2
V
CAP
4
OCR_DIS
V
DD
V
ss
7
5
V
DDA
2
V
SSA
RESET
6
3
3
6
3
4
4
4
5
4
4
PWM Outputs
Current Sense Inputs
or GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
PWMA
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
R/W Control
XDB2
XAB1
XAB2
PAB
6
External
Address Bus
Switch
2
8
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
Boot ROM
8K x 16 Flash
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
AD1
TEMP_SENSE
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
External Bus
Interface Unit
4
Data Memory
4K x 16 Flash
4K x 16 RAM
PDB
CDBR
CDBW
System Bus
Control
7
External Data
Bus Switch
9
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
4
IPBus Bridge (IPBB)
Decoding
Peripherals
Clock
resets
Bus Control
2
GPIOD0-1 or CS2-3
PS or CS0 or GPIOD8
DS or CS1 or GPIOD9
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
1
2
2
PLL
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA IRQB
CLKO CLKMODE
56F8356 Block Diagram
漏 Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com

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