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56F8345 Datasheet

  • 56F8345

  • 56F8345 16-bit Hybrid Controller

  • 1422.43KB

  • 148頁(yè)

  • MOTOROLA   MOTOROLA

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Freescale Semiconductor, Inc.
MC56F8345/D
Rev. 8.0, 6/2004
56F8345
Preliminary Technical Data
56F8345 16-bit Hybrid Controller
鈥?Up to 60 MIPS at 60MHz core frequency
鈥?DSP and MCU functionality in a unified,
C-efficient architecture
鈥?128KB Program Flash
鈥?Two Quadrature Decoders
鈥?FlexCAN module
鈥?Optional On-Chip Regulator
鈥?Two Serial Communication Interfaces (SCIs)
鈥?Up to two Serial Peripheral Interface (SPIs)
鈥?Up to four general-purpose Quad Timers
鈥?Computer Operating Properly (COP)/Watchdog
鈥?JTAG/Enhanced On-Chip Emulation (OnCE鈩? for
unobtrusive, real-time debugging
鈥?Up to 49 GPIO lines
鈥?128-pin LQFP Package
RSTO
RESET
6
PWM Outputs
3
4
Current Sense Inputs
or GPIOC
Fault Inputs
Program Controller
and Hardware
Looping Unit
Freescale Semiconductor, Inc...
鈥?4KB Program RAM
鈥?8KB Data Flash
鈥?8KB Data RAM
鈥?8KB Boot Flash
鈥?Two 6-channel PWM modules
鈥?Four 4-channel, 12-bit ADCs
鈥?Temperature Sensor
V
PP
5
JTAG/
EOnCE
Port
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
2
PWMA
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
6
PWM Outputs
3
4
4
4
5
4
4
Current Sense Inputs
or GPIOD
Fault Inputs
Address
Generation Unit
PWMB
Data ALU
16 x 16 + 36 -->36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
AD0
ADCA
AD1
VREF
PAB
PDB
CDBR
CDBW
Memory
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
AD0
ADCB
AD1
TEMP_SENSE
4
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SP1I or
GPIOC
Quad Timer
C or GPIOE
Quad Timer
D or GPIOE
FlexCAN
System Bus
Control
External Bus
Interface Unit
*
External
Address Bus
Switch
6
5
A8-13 or GPIOA0-5
GPIOB0-4 or A16-20
*
External
Data
Bus Switch
4
D7-10 or GPIOF0-3
*
Bus
Control
6
GPIOD0-5 or CS2-7
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
2
Decoding
Peripherals
4
2
Clock
resets
P
System
O
Integration
R
Module
PLL
*
EMI not functional in
this package; use as
GPIO pins
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Interrupt
Watchdog Controller
Clock
O
S
Generator
C
CLKMODE
XTAL
EXTAL
IRQA IRQB
CLKO
56F8345 Block Diagram - 128 LQFP
漏 Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com

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