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54LS113FMQB Datasheet

  • 54LS113FMQB

  • Dual JK Edge-Triggered Flip-Flop

  • 6頁

  • NSC

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54LS113 Dual JK Edge-Triggered Flip-Flop
June 1989
54LS113
Dual JK Edge-Triggered Flip-Flop
General Description
The 54LS113 offers individual J K Set and Clock inputs
When the clock goes HIGH the inputs are enabled and data
may be entered The logic level of the J and K inputs may
be changed when the clock pulse is HIGH and the bistable
will perform according to the Truth Table as long as mini-
mum setup and hold times are observed Input data is trans-
ferred to the outputs on the falling edge of the clock pulse
Connection Diagram
Dual-In-Line Package
Logic Symbol
TL F 10205 鈥?2
TL F 10205 鈥?1
V
CC
e
Pin 14
GND
e
Pin 7
Order Number 54LS113DMQB
54LS113FMQB or 54LS113LMQB
See NS Package Number E20A J14A or W14B
Truth Table
Inputs
t
n
J
L
L
H
H
K
L
H
L
H
Output
t
n
a
1
Q
Q
n
L
H
Q
n
Pin Names
J1 J2 K1 K2
CP1 CP2
SD1 SD2
Q1 Q2 Q1 Q2
Description
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
t
n
e
Bit Time before Clock Pulse
t
n
a
1
e
Bit Time after Clock Pulse
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
Asynchronous Input
Low input to S
D
sets Q to HIGH level
Set is independent of clock
C
1995 National Semiconductor Corporation
TL F 10205
RRD-B30M105 Printed in U S A

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