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54LS03 Datasheet

  • 54LS03

  • Quad 2-Input NAND Gates with Open-Collector Outputs

  • 130.96KB

  • 7頁

  • NSC

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54LS03 DM54LS03 DM74LS03 Quad 2-Input NAND Gates with Open-Collector Outputs
June 1989
54LS03 DM54LS03 DM74LS03
Quad 2-Input NAND Gates
with Open-Collector Outputs
General Description
This device contains four independent gates each of which
performs the logic NAND function The open-collector out-
puts require external pull-up resistors for proper logical op-
eration
Pull-Up Resistor Equations
R
MAX
e
V
CC
(Min)
b
V
OH
N
1
(I
OH
)
a
N
2
(I
IH
)
Features
Y
V
CC
(Max)
b
V
OL
R
MIN
e
I
OL
b
N
3
(I
IL
)
Where N
1
(I
OH
)
e
total maximum output high current for all
outputs tied to pull-up resistor
N
2
(I
IH
)
e
total maximum input high current for all
inputs tied to pull-up resistor
N
3
(I
IL
)
e
total maximum input low current for all
inputs tied to pull-up resistor
Alternate Military Aerospace device (54LS03) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram
Dual-In-Line Package
TL F 6344 鈥?1
Order Number 54LS03DMQB 54LS03FMQB 54LS03LMQB
DM54LS03J DM54LS03W DM74LS03M or DM74LS03N
See NS Package Number E20A J14A M14A N14A or W14B
Function Table
Y
e
AB
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
H
e
High Logic Level
L
e
Low Logic Level
C
1995 National Semiconductor Corporation
TL F 6344
RRD-B30M105 Printed in U S A

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