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54HSC Datasheet

  • 54HSC

  • Radiation hard 16-Bit ParallelError Detection & Correction

  • 10頁

  • DYNEX

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54HSC/T630
54HSC/T630
Radiation hard 16-Bit ParallelError
Detection & Correction
Replaces June 1999 version, DS3595-4.0
DS3595-5.0 January 2000
The 54HSC/T630 is a 16-bit parallel Error Detection and
Correction circuit. It uses a modified Hamming code to
generate a 6-bit check word from each 16-bit data word. The
check word is stored with the data word during a memory write
cycle. During a memory read cycle a 22-bit word is taken from
memory and checked for errors.
Single bit errors in data words are flagged and corrected.
Single bit errors in check words are flagged but not corrected.
The position of the incorrect bit is pinpointed, in both cases, by
the 6-bit error syndrome code which is output during the error
correction cycle.
Two bit errors are flagged but not corrected. Any
combination of two bit errors occurring within the 22-bit word
read from memory, (ie two errors in the 16-bit data word, two
bits in the 16-bit check word or one error in each) will be
correctly identified.
The gross errors of all bits, low or high, will be detected.
The control signals S1 and S0 select the function to be
performed by the EDAC They control the generation of check
words and the latching and correction of data (see table 1)
When errors are detected, flags are placed on outputs SEF
and DEF (see table 2).
Figure 1: Block Diagram
FEATURES
s
Radiation Hard:
Dose Rate Upset Exceeding 3x10
10
Rad(Si)/sec
Total Dose for Functionality Upto 1x10
6
Rad(Si)
s
High SEU Immunity, Latch Up Free
s
CMOS-SOS Technology
s
All Inputs and Outputs Fully TTL Compatible (54HST630)
or CMOS Compatible (54HSC630)
s
Low Power
s
Detects and Corrects Single-Bit Errors
s
Detects and Flags Dual-Bit Errors
s
High Speed:
Write Cycle - Generates Checkword In 40ns Typical
Read Cycle - Flags Errors In 20ns Typical
1/10

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