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54FCT373DMQB Datasheet

  • 54FCT373DMQB

  • Octal Transparent Latch with TRI-STATE Outputs

  • 8頁

  • NSC

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54FCT373 Octal Transparent Latch with TRI-STATE Outputs
October 1999
54FCT373
Octal Transparent Latch with TRI-STATE
廬
Outputs
General Description
The 鈥橣CT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
Features
TRI-STATE outputs for bus interfacing
TTL input and output level compatible
CMOS power consumption
Output sink capability of 32 mA, source capability of
12 mA
n
Standard Microcircuit Drawing (SMD) 5962-8764401
n
n
n
n
Ordering Code
Military
54FCT373DMQB
54FCT373FMQB
54FCT373LMQB
Package Number
J20A
W20A
E20A
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
20-Lead Ceramic Dual-In-Line
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100957-2
DS100957-1
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
Description
Data Inputs
Latch Enable Input
(Active HIGH)
Output Enable Input
(Active LOW)
TRI-STATE Latch
Outputs
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1999 National Semiconductor Corporation
DS100957
www.national.com

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