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54FCT273FMQB Datasheet

  • 54FCT273FMQB

  • Octal D-Type Flip-Flop

  • 148.02KB

  • 8頁(yè)

  • NSC

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54FCT273 Octal D-Type Flip-Flop
August 1998
54FCT273
Octal D-Type Flip-Flop
General Description
The 鈥橣CT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
Eight edge-triggered D flip-flops
Buffered common clock
Buffered, asynchronous Master Reset
See 鈥橣CT377 for clock enable version
See 鈥橣CT373 for transparent latch version
See 鈥橣CT374 for TRI-STATE
廬
version
Output sink capability of 32 mA, source capability of
12 mA
n
TTL input and output level compatible
n
CMOS power consumption
n
Standard Microcircuit Drawing (SMD) 5962-8765601
n
n
n
n
n
n
n
Ordering Code
Military
54FCT273DMQB
54FCT273FMQB
54FCT273LMQB
J20A
W20A
E20A
Package
Number
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
Connection Diagrams
Pin Assignment for DIP
and Flatpack
Pin Assignment
for LCC
DS100956-2
DS100956-1
Pin
Names
D
0
鈥揇
7
MR
CP
Q
0
鈥換
7
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
Description
Data Inputs
Master Reset
(Active LOW)
Clock Pulse Input
(Active Rising Edge)
Data Outputs
漏 1998 National Semiconductor Corporation
DS100956
www.national.com

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