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54FCT138 Datasheet

  • 54FCT138

  • 1-of-8 Decoder/Demultiplexer

  • 7頁

  • NSC

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54FCT138 1-of-8 Decoder/Demultiplexer
October 1999
54FCT138
1-of-8 Decoder/Demultiplexer
General Description
The FCT138 is a high-speed 1-of-8 decoder/demultiplexer.
This device is ideally suited for high-speed bipolar memory
chip select address decoding. The multiple input enables al-
low parallel expansion to a 1-of-24 decoder using just three
FCT138 devices or a 1-of-32 decoder using four FCT138 de-
vices and one inverter.
Features
Demultiplexing capability
Multiple input enable for easy expansion
Active LOW mutually exclusive outputs
Outputs sink capability of 32mA, source capability of
12mA
n
TTL input and output level compatible
n
CMOS power consumption
n
Standard Microcircuit Drawing (SMD) 5962-8765401
n
n
n
n
Ordering Code
Military
54FCT138DMQB
54FCT138FMQB
54FCT138LMQB
Package
Number
J16A
W16A
E20A
16-Lead Ceramic Dual-In-Line
16-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100963-1
IEEE/IEC
DS100963-2
Pin Assignment
for LCC
DS100963-7
Pin Names
A
0
鈥揂
2
E
1
鈥揈
2
E
3
O
0
鈥揙
7
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
DS100963-3
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
漏 1999 National Semiconductor Corporation
DS100963
www.national.com

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