MILITARY DATA SHEET
MN54F273-X REV 1A0
OCTAL D FLIP-FLOP
General Description
The F273 has eight edge-triggered D-type Flip-flops with individual D inputs and Q
outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input one setup time before the
LOW-to HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage
level on the MR input. The device is useful for applications where the true output only
is required, and the Clock and Master Reset are common to all storage elements.
Original Creation Date: 05/30/96
Last Update Date: 07/30/96
Last Major Revision Date: 05/30/96
Industry Part Number
54F273
NS Part Numbers
54F273DMQB
54F273FMQB
54F273LMQB
Prime Die
M273
Processing
MIL-STD-883, Method 5004
Subgrp Description
1
2
3
4
5
6
7
8A
8B
9
10
11
Static tests at
Static tests at
Static tests at
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Temp (
o
C)
+25
+125
-55
+25
+125
-55
+25
+125
-55
+25
+125
-55
Quality Conformance Inspection
MIL-STD-883, Method 5005
1