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54ALS137 Datasheet

  • 54ALS137

  • 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHE...

  • 15頁

  • TI

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SN54ALS137A, SN74ALS137A, SN74AS137
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
WITH ADDRESS LATCHES
SDAS203C 鈥?APRIL 1982 鈥?REVISED JANUARY 1995
鈥?/div>
鈥?/div>
鈥?/div>
Combines Decoder and 3-Bit Address
Latch
Incorporates Two Output Enables to
Simplify Cascading
Package Options Include Plastic Small-
Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
SN54ALS137A . . . J PACKAGE
SN74ALS137A, SN74AS137 . . . D OR N PACKAGE
(TOP VIEW)
description
The SN54ALS137A, SN74ALS137A, and
SN74AS137 are 3-line to 8-line decoders/
demultiplexers with latches on the three address
inputs. When the latch-enable (LE) input is low,
the devices act as decoders/demultiplexers.
When LE goes from low to high, the address
present at the select (A, B, and C) inputs is stored
in the latches. Further address changes are
ignored as long as LE remains high. The
output-enable controls (G1 and G2) control the
outputs independently of the select or
latch-enable inputs. All of the outputs are forced
high if G1 is low or G2 is high. These devices are
ideally suited for implementing glitch-free
decoders in strobed (stored-address) applications
in bus-oriented systems.
The SN54ALS137A is characterized for operation
over the full military temperature range of 鈥?55擄C
to 125擄C. The SN74ALS137A and SN74AS137
are characterized for operation from 0擄C to 70擄C.
FUNCTION TABLE
INPUTS
ENABLE
LE
X
X
L
L
L
L
L
L
L
L
H
G1
X
L
H
H
H
H
H
H
H
H
H
G2
H
X
L
L
L
L
L
L
L
L
L
C
X
X
L
L
L
L
H
H
H
H
X
SELECT
B
X
X
L
L
H
H
L
L
H
H
X
A
X
X
L
H
L
H
L
H
L
H
X
Y0
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
L
H
H
H
H
H
A
B
C
LE
G2
G1
Y7
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54ALS137A . . . FK PACKAGE
(TOP VIEW)
C
LE
NC
G2
G1
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
B
A
NC
V
CC
Y0
Y1
Y2
NC
Y3
Y4
NC 鈥?No internal connection
OUTPUTS
Y3
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
L
Copyright
漏
1995, Texas Instruments Incorporated
Outputs corresponding to stored address = L; all others = H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
Y7
GND
NC
Y6
Y5
1

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