54ACTQ377 Octal D Flip-Flop with Clock Enable
September 1998
54ACTQ377
Octal D Flip-Flop with Clock Enable
General Description
The ACTQ377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
The ACTQ377 utilizes FACT Quiet Series
廬
technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features GTO
廬
output control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
n
Ideal for addressable register applications
n
Clock enable for address and data synchronization
applications
n
Eight edge-triggered D flip-flops
n
Buffered common clock
n
Outputs source/sink 24 mA
n
See 鈥?73 for master reset version
n
See 鈥?73 for transparent latch version
n
See 鈥?74 for TRI-STATE
廬
version
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
TTL-compatible inputs and outputs
n
Standard Microcircuit Drawing (SMD) 5962-9219001
Logic Symbols
IEEE/IEC
DS100357-1
DS100357-2
Pin
Names
D
0
鈥揇
7
CE
Q
0
鈥換
7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
GTO
廬
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
and FACT Quiet Series
廬
are registered trademarks of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100357
www.national.com
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