54ACT283 4-Bit Binary Full Adder with Fast Carry
September 1998
54ACT283
4-Bit Binary Full Adder with Fast Carry
General Description
The 鈥橝CT283 high-speed 4-bit binary full adder with internal
carry lookahead accepts two 4-bit binary words (A
0
鈥揂
3
,
B
0
鈥揃
3
) and a Carry input (C
0
). It generates the binary Sum
outputs (S
0
鈥揝
3
) and the Carry output (C
4
) from the most sig-
nificant bit. The 鈥橝CT283 will operate with either active HIGH
or active LOW operands (positive or negative logic).
Features
n
n
n
n
Guaranteed 4000V minimum ESD protection
Outputs source/sink 24 mA
TTL-compatible inputs
Available to Mil-Std-883
Logic Symbols
Pin Assignment for LCC
DS100977-1
IEEE/IEC
DS100977-3
Functional Description
The 鈥橝CT283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C
0
). The binary sum appears on the Sum
(S
0
鈥揝
3
) and outgoing carry (C
4
) outputs. The binary weight
of the various inputs and outputs is indicated by the subscript
numbers, representing powers of two.
2
0
(A
0
+ B
0
+ C
0
) + 2
1
(A
1
+ B
1
)
+ 2
2
(A
2
+ B
2
) + 2
3
(A
3
+ B
3
)
= S
0
+ 2S
1
+ 4S
2
+ 8S
3
+ 16C
4
Where (+) = plus
Interchanging inputs of equal weight does not affect the op-
eration. Thus C
0
, A
0
, B
0
can be arbitrarily assigned to pins 5,
6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages.
Due to the symmetry of the binary add function, the 鈥橝CT283
can be used either with all inputs and outputs active HIGH
(positive logic) or with all inputs and outputs active LOW
(negative logic). See
Figure 1.
Note that if C
0
is not used it
must be tied LOW for active HIGH logic or tied HIGH for ac-
tive LOW logic.
Due to pin limitations, the intermediate carries of the
鈥橝CT283 are not brought out for use as inputs or outputs.
However, other means can be used to effectively insert a
carry into, or bring a carry out from, an intermediate stage.
Figure 2
shows how to make a 3-bit adder. Tying the oper-
and inputs of the fourth adder (A
3
, B
3
) LOW makes S
3
de-
pendent only on, and equal to, the carry from the third adder.
Using somewhat the same principle,
Figure 3
shows a way
of dividing the 鈥橝CT283 into a 2-bit and a 1-bit adder. The
third stage adder (A
2
, B
2
, S
2
) is used merely as a means of
getting a carry (C
10
) signal into the fourth stage (via A
2
and
B
2
) and bringing out the carry from the second stage on S
2
.
www.national.com
DS100977-4
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100977-2
漏 1998 National Semiconductor Corporation
DS100977
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