54ACT175F Datasheet

IC型號(hào)：
54ACT175F
PDF描述：
Quad D Flip-Flop
文件大?。?/label>
145.36KB
PDF頁(yè)數(shù)：
8頁(yè)
芯片廠家：
NSC

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54AC175

鈥?/div>

54ACT175 Quad D Flip-Flop

August 1998

54AC175

鈥?/div>

54ACT175

Quad D Flip-Flop

General Description

The 鈥橝C/鈥橝CT175 is a high-speed quad D flip-flop. The de-

vice is useful for general flip-flop requirements where clock

and clear inputs are common. The information on the D in-

puts is stored during the LOW-to-HIGH clock transition. Both

true and complemented outputs of each flip-flop are pro-

vided. A Master Reset input resets all flip-flops, independent

of the Clock or D inputs, when LOW.

Buffered positive edge-triggered clock

Asynchronous common reset

True and complement output

Outputs source/sink 24 mA

鈥橝CT175 has TTL-compatible inputs

Standard Microcircuit Drawing (SMD)

鈥?鈥橝C175: 5962-89552

鈥?鈥橝CT175: 5962-89693

Features

Edge-triggered D-type inputs

Logic Symbols

Connection Diagrams

Pin Assignment

for DIP and Flatpak

DS100278-1

IEEE/IEC

DS100278-3

Pin Assignment for LCC

DS100278-2

Pin Names

鈥揇

鈥換

Description

Data Inputs

Clock Pulse Input

Master Reset Input

True Outputs

Complement Outputs

DS100278-4

FACT

廬

is a registered trademark of Fairchild Semiconductor Corporation.

漏 1998 National Semiconductor Corporation

DS100278

www.national.com

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54ACT175F Datasheet

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