鈩?/div>
output control and un-
dershoot corrector in addition to a split ground bus for supe-
rior performance.
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n
Outputs source/sink 24 mA
n
Faster prop delays than standard 鈥橝CT573
n
4 kV minimum ESD immunity
n
Standard Microcircuit Drawing (SMD)
鈥?鈥橝CTQ573: 5962-92194
鈥?鈥橝CQ573: 5962-92180
Features
n
I
CC
and I
OZ
reduced by 50%
Logic Symbols
IEEE/IEC
DS100242-1
DS100242-2
Pin Names
D
0
鈥揇
7
LE
OE
O
0
鈥揙
7
Data Inputs
Description
Latch Enable Input
TRI-STATE Output Enable Input
TRI-STATE Latch Outputs
GTO
鈩?/div>
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100242
www.national.com
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