鈩?/div>
output control and un-
dershoot corrector in addition to a split ground bus for supe-
rior performance.
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Outputs source/sink 24 mA
n
Faster prop delays than the standard 鈥橝C/鈥橝CT244
n
4 kV minimum ESD immunity
n
Standard Microcircuit Drawing (SMD)
鈥?鈥橝CTQ244: 5962-92186
鈥?鈥橝CQ244: 5962-92176
Features
n
I
CC
and I
OZ
reduced by 50%
Logic Symbol
IEE/IEC
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100236-1
DS100236-2
Pin Names
OE
1
, OE
2
I
0
鈥揑
7
O
0
鈥揙
7
Inputs
Outputs
Description
TRI-STATE Output Enable Inputs
Pin Assignment
for LCC
DS100236-3
GTO
鈩?/div>
is a trademark of National Semiconductor Corporation.
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
鈩?/div>
is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100236
www.national.com
next