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54AC377L Datasheet

  • 54AC377L

  • Octal D Flip-Flop with Clock Enable

  • 181.34KB

  • 8頁

  • NSC

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54AC377
鈥?/div>
54ACT377 Octal D Flip-Flop with Clock Enable
February 1999
54AC377
鈥?/div>
54ACT377
Octal D Flip-Flop with Clock Enable
General Description
The 鈥橝C/鈥橝CT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
n
Ideal for addressable register applications
n
Clock enable for address and data synchronization
applications
n
Eight edge-triggered D flip-flops
n
Buffered common clock
n
Outputs source/sink 24 mA
n
See 鈥?73 for master reset version
n
See 鈥?73 for transparent latch version
n
See 鈥?74 for TRI-STATE
廬
version
n
鈥橝CT377 has TTL-compatible inputs
n
Standard Microcircuit Drawing (SMD)
鈥?鈥橝C377: 5962-88702
鈥?鈥橝CT377: 5962-87697
Features
n
I
CC
reduced by 50%
Logic Symbols
IEEE/IEC
DS100290-1
DS100290-2
Pin
Names
D
0
鈥揇
7
CE
Q
0
鈥換
7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
漏 1999 National Semiconductor Corporation
DS100290
www.national.com

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