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54AC299J Datasheet

  • 54AC299J

  • 8-Input Universal Shift/Storage Register with Common Paralle...

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54ACC299
鈥?/div>
54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
September 1998
54AC299
鈥?/div>
54ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
General Description
The 鈥橝C/鈥橝CT299 is an 8-bit universal shift/storage register
with TRI-STATE
廬
outputs. Four modes of operation are pos-
sible: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to re-
duce the total number of package pins. Additional outputs
are provided for flip-flops Q
0
, Q
7
to allow easy serial cascad-
ing. A separate active LOW Master Reset is used to reset the
register.
n
Common parallel I/O for reduced pin count
n
Additional serial inputs and outputs for expansion
n
Four operating modes: shift left, shift right, load and
store
n
TRI-STATE outputs for bus-oriented applications
n
Outputs source/sink 24 mA
n
鈥橝CT299 has TTL-compatible inputs
n
Standard Microcircuit Drawing (SMD)
鈥橝C299: 5962-88754
鈥橝CT299: 5962-88771
Features
n
I
CC
and I
OZ
reduced by 50%
Ordering Code:
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100252-1
IEEE/IEC
DS100252-2
Pin Assignment for LCC
DS100252-3
DS100252-4
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
廬
is a registered trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100252
www.national.com

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