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54ACT161
Synchronous Presettable Binary Counter
General Description
The 鈥橝C/鈥橝CT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for ap-
plication in programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output for versa-
tility in forming synchronous multistage counters. The 鈥橝C/
鈥橝CT161 has an asynchronous Master Reset input that over-
rides all other inputs and forces the outputs LOW.
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n
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Synchronous counting and loading
High-speed synchronous expansion
Typical count rate of 125 MHz
Outputs source/sink 24 mA
鈥橝CT161 has TTL-compatible inputs
Standard Microcircuit Drawing (SMD)
鈥?鈥橝C161: 5962-89561
鈥?鈥橝CT161: 5962-91722
Features
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I
CC
reduced by 50%
Logic Symbols
Pin Names
CEP
CET
CP
MR
P
0
鈥揚(yáng)
3
PE
Q
0
鈥換
3
TC
DS100274-1
Description
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input
Asynchronous Master Reset Input
Parallel Data Inputs
Parallel Enable Inputs
Flip-Flop Outputs
Terminal Count Output
IEEE/IEC
DS100274-2
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
FACT
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is a trademark of Fairchild Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100274
www.national.com
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