鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), DIP
(N) Packages, Ceramic Chip Carriers (FK),
Flat (W), and DIP (J) Packages
SN54AC00 . . . J OR W PACKAGE
SN74AC00 . . . D, DB, N, OR PW PACKAGE
(TOP VIEW)
description
The 鈥楢C00 contain four independent 2-input NAND
gates. Each gate performs the Boolean function of
Y = A
S
B or Y = A + B in positive logic.
The SN54AC00 is characterized for operation over
the full military temperature range of 鈥?55擄C to 125擄C.
The SN74AC00 is characterized for operation from
鈥?40擄C to 85擄C.
FUNCTION TABLE
(each gate)
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
SN54AC00 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2A
NC
2B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1B
1A
NC
V
CC
4B
4A
NC
4Y
NC
3B
NC 鈥?No internal connection
A
logic symbol
鈥?/div>
1A
1B
2A
2B
3A
3B
4A
4B
1
2
4
5
9
10
12
13
11
4Y
8
3Y
6
2Y
logic diagram (positive logic)
&
3
1Y
Y
B
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, N, PW, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
1
2
3
4
5
