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54ABT377W-QML Datasheet

  • 54ABT377W-QML

  • Octal D-Type Flip-Flop with Clock Enable

  • 8頁(yè)

  • NSC

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54ABT377 Octal D-Type Flip-Flop with Clock Enable
July 1998
54ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The 鈥橝BT377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
n
n
n
n
n
n
n
n
n
n
n
Eight edge-triggered D flip-flops
Buffered common clock
See 鈥橝BT273 for master reset version
See 鈥橝BT373 for transparent latch version
See 鈥橝BT374 for TRI-STATE
廬
version
Output sink capability of 48 mA, source capability of
24 mA
Guaranteed latchup protection
High impedance glitch free bus loading during entire
power up and power down cycle
Non-destructive hot insertion capability
Disable time less than enable time to avoid bus
contention
Standard Microcircuit Drawing (SMD) 5962-9314801
Features
n
Clock enable for address and data synchronization
applications
Ordering Code:
Military
54ABT377J-QML
54ABT377W-QML
54ABT377E-QML
Package
Number
J20A
W20A
E20A
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Package Description
Connection Diagram
Pin Assignment for
DIP and Cerpack
Pin Assignment for LCC
DS100216-11
DS100216-1
Pin
Names
D
0
鈥揇
7
CE
CP
Q
0
鈥換
7
Data Inputs
Description
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
TRI-STATE
廬
is a registered trademark of National Semiconductor Corporation.
漏 1998 National Semiconductor Corporation
DS100216
www.national.com

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