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534HD622M080BG Datasheet

  • 534HD622M080BG

  • VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 G...

  • 12頁

  • SILABS

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Si550
P
R E L I M I N A R Y
D
A TA
S
H E E T
V
O L TA G E
- C
O N T R O L L E D
C
R Y S TA L
O
S C I L L A T O R
(V CX O)
10 MH
Z T O
1.4 G H
Z
Features
Available with any-rate output
frequencies from 10 MHz to
945 MHz and selected frequencies
to 1.4 GHz
3rd generation DSPLL
廬
with
superior jitter performance
3x better frequency stability than
SAW based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, & CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
Si5602
Ordering Information:
See page 8.
Applications
SONET / SDH
xDSL
10 GbE LAN / WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 7.
(Top View)
V
C
1
2
3
6
5
4
V
DD
Description
The Si550 VCXO utilizes Silicon Laboratories鈥?advanced DSPLL
廬
circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXO鈥檚 where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating long lead times associated with custom oscillators.
OE
GND
CLK鈥?/div>
CLK+
Functional Block Diagram
V
DD
CLK鈥?/div>
CLK+
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL
廬
Clock Synthesis
ADC
Vc
OE
GND
Preliminary Rev. 0.3 4/06
Copyright 漏 2006 by Silicon Laboratories
Si550
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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