4 MEG x 16
EDO DRAM
EDO DRAM
FEATURES
鈥?Single +3.3V 鹵0.3V power supply
鈥?Industry-standard x16 pinout, timing, functions,
and package
鈥?12 row, 10 column addresses (4)
13 row, 9 column addresses (8)
鈥?High-performance CMOS silicon-gate process
鈥?All inputs, outputs and clocks are LVTTL-compatible
鈥?Extended Data-Out (EDO) PAGE MODE access
鈥?4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
鈥?Self refresh for low-power data retention
4X16E43V
PIN ASSIGNMENT (Top View)
50-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
V
CC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
V
CC
鈥?/div>
A12
OPTIONS
鈥?Plastic Package
50-pin TSOP (400 mil)
鈥?Timing
50ns access
60ns access
鈥?Refresh Rates
4K
8K
鈥?Operating Temperature Range
Commercial (0擄C to +70擄C)
Extended (-40擄C to +85擄C)
MARKING
TW
-5
-6
4
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
V
SS
CASL#
CASH#
OE#
NC
NC
NC/A12
鈥?/div>
A11
A10
A9
A8
A7
A6
V
SS
for "8K" version, NC for "4K" version.
4X16E43V
4X16E83V
None
IT
Configuration
Refresh
Row Address
Column Addressing
4 Meg x 16
4K
4K (A0-A11)
1K (A0-A9)
4 Meg x 16
8K
8K (A0-A12)
512 (A0-A8)
NOTE:
1. The 鈥?鈥?symbol indicates signal is active LOW.
4 MEG x 16 EDO DRAM PART NUMBERS
Part Number Example:
MEM4X16E43VTW-5
PART NUMBER
4X16E43VTW-x
4X16E83VTW-x
t
CAC
t
CAS
REFRESH
ADDRESSING
4
8
PACKAGE
400-TSOP
400-TSOP
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
x = speed
1
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