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IS42S32200

512K Bits x 32 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

FEATURES

鈥?Clock frequency: 166, 143 MHz

鈥?Fully synchronous; all signals referenced to a

positive clock edge

鈥?Internal bank for hiding row access/precharge

鈥?Single 3.3V power supply

鈥?LVTTL interface

鈥?Programmable burst length

鈥?(1, 2, 4, 8, full page)

鈥?Programmable burst sequence:

Sequential/Interleave

鈥?Self refresh modes

鈥?4096 refresh cycles every 64 ms

鈥?Random column address every clock cycle

鈥?Programmable

CAS

latency (2, 3 clocks)

鈥?Burst read/write and burst read/single write

operations capability

鈥?Burst termination by burst stop and precharge

command

鈥?Industrial temperature availability

鈥?Package 400-mil 86-pin TSOP II

ISSI

PIN CONFIGURATION

(86-Pin TSOP (Type II)

廬

PRELIMINARY INFORMATION

August 2003

OVERVIEW

ISSI

's 64Mb Synchronous DRAM IS42S32200 is organized

as 524,288 bits x 32-bit x 4-bank for improved performance.

The synchronous DRAMs achieve high-speed data transfer

using pipeline architecture. All inputs and outputs signals

refer to the rising edge of the clock input.

VCC

I/O0

VCCQ

I/O1

I/O2

GNDQ

I/O3

I/O4

VCCQ

I/O5

I/O6

GNDQ

I/O7

NC

VCC

DQM0

WE

CAS

RAS

CS

NC

BA0

BA1

A10/AP

A0

A1

A2

DQM2

VCC

NC

I/O16

GNDQ

I/O17

I/O18

VCCQ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

GND

I/O15

GNDQ

I/O14

I/O13

VCCQ

I/O12

I/O11

GNDQ

I/O10

I/O9

VCCQ

I/O8

NC

GND

DQM1

NC

NC

CLK

CKE

A9

A8

A7

A6

A5

A4

A3

DQM3

GND

NC

I/O31

VCCQ

I/O30

I/O29

GNDQ

I/O28

I/O27

VCCQ

I/O26

I/O25

GNDQ

I/O24

GND

PIN DESCRIPTIONS

A0-A10

BA0, BA1

I/O0 to I/O31

CLK

CKE

CS

RAS

CAS

WE

Address Input

Bank Select Address

Data I/O

System Clock Input

Clock Enable

Chip Select

Row Address Strobe Command

Column Address Strobe Command

Write Enable

I/O19

I/O20

GNDQ

I/O21

I/O22

VCCQ

I/O23

VCC

Vcc

GND

Vcc

Q

GND

Q

NC

Power

Ground

Power Supply for I/O Pin

Ground for I/O Pin

No Connection

DQM0 to DQM3 Input/Output Mask

Copyright 漏 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. 鈥?1-800-379-4774

PRELIMINARY INFORMATION

08/14/03

Rev. 00B

1

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  512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC ...
  
  42S32200
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  英文版
  512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC ...
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