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42S16400A Datasheet

  • 42S16400A

  • 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC...

  • 469.96KB

  • 55頁(yè)

  • ISSI   ISSI

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IS42S16400A
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
鈥?Clock frequency:166, 133, 100 MHz
鈥?Fully synchronous; all signals referenced to a
positive clock edge
鈥?Internal bank for hiding row access/precharge
鈥?Single 3.3V power supply
鈥?LVTTL interface
鈥?Programmable burst length
鈥?(1, 2, 4, 8, full page)
鈥?Programmable burst sequence:
Sequential/Interleave
鈥?Self refresh modes
鈥?4096 refresh cycles every 64 ms
鈥?Random column address every clock cycle
鈥?Programmable
CAS
latency (2, 3 clocks)
鈥?Burst read/write and burst read/single write
operations capability
鈥?Burst termination by burst stop and precharge
command
鈥?Byte controlled by LDQM and UDQM
鈥?Industrial temperature availability
(133MHz, 100MHz)
鈥?Package: 400-mil 54-pin TSOP II,
a lead-free package is available.
ISSI
April 2003
廬
OVERVIEW
ISSI
's 64Mb Synchronous DRAM IS42S16400A is organized
as 1,048,576 bits x 16-bit x 4-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
54-Pin TSOP (Type II)
VCC
I/O0
VCCQ
I/O1
I/O2
GNDQ
I/O3
I/O4
VCCQ
I/O5
I/O6
GNDQ
I/O7
VCC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
GND
I/O15
GNDQ
I/O14
I/O13
VCCQ
I/O12
I/O11
GNDQ
I/O10
I/O9
VCCQ
I/O8
GND
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
BA0, BA1
I/O0 to I/O15
CLK
CKE
CS
RAS
CAS
Address Input
Bank Select Address
Data I/O
System Clock Input
Clock Enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LDQM
UDQM
Vcc
GND
Vcc
Q
GND
Q
NC
Write Enable
Lower Bye, Input/Output Mask
Upper Bye, Input/Output Mask
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Copyright 漏 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. 鈥?www.issi.com 鈥?/div>
1-800-379-4774
Rev.C
04/16/03
1

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