CD4051BM CD4051BC CD4052BM CD4052BC CD4053BM CD4053BC
Analog Multiplexer Demultiplexers
October 1989
CD4051BM CD4051BC Single 8-Channel Analog
Multiplexer Demultiplexer
CD4052BM CD4052BC Dual 4-Channel Analog
Multiplexer Demultiplexer
CD4053BM CD4053BC Triple 2-Channel Analog
Multiplexer Demultiplexer
General Description
These analog multiplexers demultiplexers are digitally con-
trolled analog switches having low 鈥樷€極N鈥欌€?impedance and
very low 鈥樷€極FF鈥欌€?leakage currents Control of analog signals
up to 15V
p-p
can be achieved by digital signal amplitudes of
3鈥?5V For example if V
DD
e
5V V
SS
e
0V and V
EE
eb
5V
analog signals from
b
5V to
a
5V can be controlled by digi-
tal inputs of 0鈥?V The multiplexer circuits dissipate ex-
tremely low quiescent power over the full V
DD
b
V
SS
and
V
DD
b
V
EE
supply voltage ranges independent of the logic
state of the control signals When a logical 鈥樷€?鈥欌€?is present at
the inhibit input terminal all channels are 鈥樷€極FF鈥欌€?/div>
CD4051BM CD4051BC is a single 8-channel multiplexer
having three binary control inputs A B and C and an inhibit
input The three binary signals select 1 of 8 channels to be
turned 鈥樷€極N鈥欌€?and connect the input to the output
CD4052BM CD4052BC is a differential 4-channel multiplex-
er having two binary control inputs A and B and an inhibit
input The two binary input signals select 1 or 4 pairs of
channels to be turned on and connect the differential ana-
log inputs to the differential outputs
CD4053BM CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs A B and C and
an inhibit input Each control input selects one of a pair of
channels which are connected in a single-pole double-throw
configuration
Features
Y
Y
Y
Y
Y
Y
Y
Wide range of digital and analog signal levels digital
3 鈥?15V analog to 15V
p-p
Low 鈥樷€極N鈥欌€?resistance 80X (typ ) over entire 15V
p-p
sig-
nal-input range for V
DD
b
V
EE
e
15V
High 鈥樷€極FF鈥欌€?resistance channel leakage of
g
10 pA
(typ ) at V
DD
b
V
EE
e
10V
Logic level conversion for digital addressing signals of
3 鈥?15V (V
DD
b
V
SS
e
3鈥?15V) to switch analog signals to
15 V
p-p
(V
DD
b
V
EE
e
15V)
Matched switch characteristics
DR
ON
e
5X (typ ) for
V
DD
b
V
EE
e
15V
Very low quiescent power dissipation under all digital-
control input and supply conditions 1
mW
(typ ) at
V
DD
b
V
SS
e
V
DD
b
V
EE
e
10V
Binary address decoding on chip
Connection Diagrams
Dual-In-Line Packages
CD4051BM CD4051BC
CD4052BM CD4052BC
CD4053BM CD4053BC
TL F 5662 鈥?1
Order Number CD4051B CD4052B or CD4053B
C
1995 National Semiconductor Corporation
TL F 5662
RRD-B30M105 Printed in U S A
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