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4015B Datasheet

  • 4015B

  • CMOS Dual 4-Stage Static Shift Register With Serial Input/Pa...

  • 121.67KB

  • 8頁

  • INTERSIL   INTERSIL

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CD4015BMS
December 1992
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Pinout
CD4015BMS
TOP VIEW
CLOCK B 1
Q4B 2
Q3A 3
Q2A 4
Q1A 5
RESET A 6
DATA A 7
16 VDD
15 DATA B
14 RESET B
13 Q1B
12 Q2B
11 Q3B
10 Q4A
9 CLOCK A
Features
鈥?High-Voltage Type (20V Rating)
鈥?Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V
鈥?Fully Static Operation
鈥?8 Master-Slave Flip-Flops Plus Input and Output Buffering
鈥?100% Tested For Quiescent Current at 20V
鈥?5V, 10V and 15V Parametric Ratings
鈥?Standardized Symmetrical Output Characteristics
鈥?Maximum Input Current of 1碌A(chǔ) at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and 25
o
C
鈥?Noise Margin (Full Package-Temperature Range) =
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
鈥?Meets All Requirements of JEDEC Tentative Standard
No. 13B, 鈥淪tandard Speci鏗乧ations for Description of
鈥楤鈥?Series CMOS Devices鈥?/div>
VSS 8
Functional Diagram
VDD
16
DATA A
CLOCK A
RESET A
7
9
6
4
STAGE
5
4
3
10
DATA B
15
1
14
RESET B
4
STAGE
13
12
Q2B
11
Q3B
2
Q4B
8
VSS
Q1A
Q2A
Q3A
Q4A
Q1B
Applications
鈥?Serial-Input/Parallel-Output Data Queueing
鈥?Serial to Parallel Data Conversion
鈥?General-Purpose Register
Description
CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde-
pendent CLOCK and RESET inputs as well as a single serial
DATA input. 鈥淨鈥?outputs are available from each of the four
stages on both registers. All register stages are D type, mas-
ter-slave 鏗俰p-鏗俹ps. The logic level present at the DATA input
is transferred into the 鏗乺st register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS鈥檚 is possible.
The CD4015BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
CLOCK B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
File Number
3295
7-89

4015B 產(chǎn)品屬性

  • 677現(xiàn)貨

  • 1 : ￥9.25000盒

  • -

  • 盒

  • 在售

  • 扣眼

  • 線纜，導(dǎo)線

  • 0.040" ~ 0.160"（1.02mm ~ 4.06mm）

  • 圓形 - 0.630"（16.00mm）

  • 0.200" ~ 0.280"（5.08mm ~ 7.11mm）

  • -

  • 三元乙丙橡膠（EPDM）

  • 黑色

  • -

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