CD4014BM CD4014BC 8-Stage Static Shift Register
February 1988
CD4014BM CD4014BC 8-Stage Static Shift Register
General Description
The CD4014BM CD4014BC is an 8-stage parallel input se-
rial output shift register A parallel serial control input en-
ables individual JAM inputs to each of 8 stages Q outputs
are available from the sixth seventh and eighth stages All
outputs have equal source and sink current capabilities and
conform to standard 鈥樷€楤鈥欌€?series output drive
When the parallel serial control input is in the logical 鈥樷€?鈥欌€?/div>
state data is serially shifted into the register synchronously
with the positive transition of the clock When the parallel
serial control input is in the logical 鈥樷€?鈥欌€?state data is jammed
into each stage of the register synchronously with the posi-
tive transition of the clock
All inputs are protected against static discharge with diodes
to V
DD
and V
SS
Features
Y
Y
Y
Y
Y
Y
Wide supply voltage range
3 0V to 15V
High noise immunity
0 45 V
DD
(typ )
Low power TTL
Fan out of 2 driving 74L
compatibility
or 1 driving 74LS
5V鈥?10V鈥?15V parametric ratings
Symmetrical output characteristics
Maximum input leakage
1
mA
at 15V over full temperature range
Connection Diagram
Dual-In-Line Package
Truth Table
Parallel
Serial
Q1
CL
Serial PI 1 PI n
Q
n
Input
(Internal)
Control
L
L
L
L
L
L
K
X
X
X
X
0
1
X
1
1
1
1
0
0
X
0
1
0
1
X
X
X
0
0
1
1
X
X
X
0
1
0
1
0
1
Q1
0
0
1
1
Q
n
b
1
Q
n
b
1
Q
n
No Change
Level change
X
e
Don鈥檛 care case
Order Number CD4014B
TL F 5947 鈥?1
Top View
Logic Diagram
TL F 5947 鈥?2
C
1995 National Semiconductor Corporation
TL F 5947
RRD-B30M105 Printed in U S A
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