3N165, 3N166
MONOLITHIC DUAL P-CHANNEL
Linear Integrated Systems
FEATURES
VERY HIGH INPUT IMPEDANCE
HIGH GATE BREAKDOWN
ULTRA LOW LEAKAGE
LOW CAPACITANCE
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
(T
A
= 25擄C unless otherwise noted)
Drain-Source or Drain-Gate Voltage
(NOTE 2)
3N165
3N166
Transient G-S Voltage
(NOTE 3)
Gate-Gate Voltage
Drain Current
(NOTE 2)
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec.)
Power Dissipation (One Side)
Total Derating above 25擄C
40 V
30 V
鹵125
V
鹵80
V
50 mA
-65擄C to +200擄C
-55擄C to +150擄C
+300擄C
300 mW
4.2 mW/擄C
ENHANCEMENT MODE
MOSFET
1
7
C
G1
G2
D2
S
3
5
D1
8 4
Device Schematic
TO-99
Bottom View
ELECTRICAL CHARACTERISTICS (T
A
=25
擄
C and V
BS
=0 unless otherwise specified)
SYMBOL
I
GSSR
I
GSSF
I
DSS
I
SDS
I
D(on)
V
GS(th)
V
GS(th)
r
DS(on)
g
fs
g
os
C
iss
C
rss
C
oss
R
E
(Y
fs
)
CHARACTERISTICS
Gate Reverse Leakage Current
Gate Forward Leakage Current
Drain to Source Leakage Current
Source to Drain Leakage Current
On Drain Current
Gate Source Threshold Voltage
Gate Source Threshold Voltage
Drain Source ON Resistance
Forward Transconductance
Output Admittance
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
LIMITS
MIN. MAX.
--
--
--
--
--
-5
-2
-2
--
1500
--
--
--
--
10
-10
-25
-200
-400
-30
-5
-5
300
3000
300
3.0
0.7
3.0
--
碌s
pF
V
DS
= -15V
(NOTE 4)
V
DS
= -15V
(NOTE 4)
I
D
= -10mA
f=100MHz
I
D
= -10mA
f=1MHz
mA
V
V
ohms
碌s
碌s
pA
UNITS
V
GS
= 40 V
V
GS
= -40 V
T
A
=+125擄C
V
DS
= -20 V
V
SD
= -20 V
V
DS
= -15 V
V
DS
= -15 V
V
DS
= V
GS
V
GS
= -20 V
V
DS
= -15V
V
DB
= 0
V
GS
= -10 V
I
D
= -10
碌A(chǔ)
I
D
= -10
碌A(chǔ)
I
D
= -100
碌A(chǔ)
I
D
= -10mA
f=1kHz
CONDITIONS
Common Source Forward Transconductance
1200
Linear Integrated Systems
4042 Clipper Ct., Fremont, CA 94538 TEL: (510) 490-9160 鈥?FAX: (510) 353-0261
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