鈥?/div>
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
10 through 500ns
Delay tolerance:
2% or 1.0ns
Temperature stability:
鹵3%
typical (0C-70C)
Vdd stability:
鹵1%
typical (4.75V-5.25V)
Minimum input pulse width:
20% of total
delay
14-pin DIP available as drop-in replacement for
hybrid delay lines
I1
I2
I3
GND
1
2
3
4
8
7
6
5
data
3
廬
delay
devices,
inc.
PACKAGES
VDD
O1
O2
O3
I1
N/C
I2
N/C
I3
N/C
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
N/C
O1
N/C
O2
N/C
O3
3D7303M DIP
3D7303H Gull-Wing
(300 Mil)
I1
I2
I3
GND
1
2
3
4
8
7
6
5
VDD
O1
O2
O3
3D7303Z SOIC
(150 Mil)
3D7303 DIP
3D7303G Gull-Wing
3D7303K Unused pins
removed
(300 Mil)
FUNCTIONAL DESCRIPTION
The 3D7303 Triple Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains three matched,
independent delay lines. Delay values can range from 10ns through
500ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D7303
is TTL- and CMOS-compatible, capable of driving ten 74LS-type
loads, and features both rising- and falling-edge accuracy.
PIN DESCRIPTIONS
I1
I2
I3
O1
O2
O3
VCC
GND
N/C
Delay Line 1 Input
Delay Line 2 Input
Delay Line 3 Input
Delay Line 1 Output
Delay Line 2 Output
Delay Line 3 Output
+5 Volts
Ground
No Connection
The all-CMOS 3D7303 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DIP-8
3D7303M
3D7303H
-10
-15
-20
-25
-30
-40
-50
-100
-200
-300
-400
-500
NOTE:
PART NUMBER
SOIC-8
DIP-14
3D7303Z
3D7303
3D7303G
-10
-10
-15
-15
-20
-20
-25
-25
-30
-30
-40
-40
-50
-50
-100
-100
-200
-200
-300
-300
-400
-400
-500
-500
DIP-14
3D7303K
-10
-15
-20
-25
-30
-40
-50
-100
-200
-300
-400
-500
DELAY
PER LINE
(ns)
10
鹵
1.0
15
鹵
1.0
20
鹵
1.0
25
鹵
1.0
30
鹵
1.0
40
鹵
1.0
50
鹵
1.0
100
鹵
2.0
200
鹵
4.0
300
鹵
6.0
400
鹵
8.0
500
鹵
10.0
Max Operating
Frequency
33.3 MHz
22.2 MHz
16.7 MHz
13.3 MHz
11.1 MHz
8.33 MHz
6.67 MHz
3.33 MHz
1.67 MHz
1.11 MHz
0.83 MHz
0.67 MHz
INPUT RESTRICTIONS
Absolute Max
Min Operating
Oper. Freq.
Pulse Width
100.0 MHz
100.0 MHz
100.0 MHz
83.3 MHz
71.4 MHz
62.5 MHz
50.0 MHz
25.0 MHz
12.5 MHz
8.33 MHz
6.25 MHz
5.00 MHz
15.0 ns
22.5 ns
30.0 ns
37.5 ns
45.0 ns
60.0 ns
75.0 ns
150.0 ns
300.0 ns
450.0 ns
600.0 ns
750.0 ns
Absolute Min
Oper. P.W.
5.0 ns
5.0 ns
5.0 ns
6.0 ns
7.0 ns
8.0 ns
10.0 ns
20.0 ns
40.0 ns
60.0 ns
80.0 ns
100.0 ns
Any delay between 10 and 500 ns not shown is also available.
漏
1996 Data Delay Devices
Doc #96001
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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