鈥?/div>
All-silicon, low-power 5V CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
1ns through 250ns
Delay tolerance:
2% or 1ns
Temperature stability:
鹵1%
typical (0C-70C)
Vdd stability:
鹵0.5%
typical (3.0V-3.6V)
Static Idd:
1.5ma typical
Minimum input pulse width:
20% of total delay
IN
O2
O4
GND
1
2
3
4
8
7
6
5
PACKAGES
VDD
O1
O3
O5
IN
O2
O4
GND
1
2
3
4
8
7
6
5
VDD
O1
O3
O5
3D7215Z-xx
SOIC
(150 Mil)
3D7215M-xx DIP (300 Mil)
For mechanical dimensions, click
here
.
For package marking details, click
here
.
FUNCTIONAL DESCRIPTION
The 3D7215 5-Tap Delay Line product family consists of fixed-delay 5V
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 1ns through 50ns. The input
is reproduced at the outputs without inversion, shifted in time as per the
user-specified dash number. The 3D7215 is 5V CMOS-compatible and
features both rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
VDD
GND
N/C
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+5 Volts
Ground
No Connection
The all-CMOS 3D7215 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered in
a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH #
3D7215Z-xx
3D7215M-xx
-1
-1.5
-2
-2.5
-3
-4
-5
-6
-8
-10
-12
-15
-20
-25
-30
-40
-50
DELAY SPECIFICATIONS
TOTAL
TAP-TAP
DELAY (ns)
DELAY (ns)
4.0
鹵
1.0*
1.0
鹵
0.5
6.0
鹵
1.0*
1.5
鹵
0.7
8.0
鹵
1.0*
2.0
鹵
0.8
10.0
鹵
1.0*
2.5
鹵
1.0
12.0
鹵
1.0*
3.0
鹵
1.3
16.0
鹵
1.0*
4.0
鹵
1.3
20.0
鹵
1.0*
5.0
鹵
1.4
24.0
鹵
1.0*
6.0
鹵
1.4
40.0
鹵
1.0
8.0
鹵
1.4
50.0
鹵
1.0
10.0
鹵
1.5
60.0
鹵
1.2
12.0
鹵
1.5
75.0
鹵
1.5
15.0
鹵
1.5
100
鹵
2.0
20.0
鹵
2.0
125
鹵
2.5
25.0
鹵
2.5
150
鹵
3.0
30.0
鹵
3.0
200
鹵
4.0
40.0
鹵
4.0
250
鹵
5.0
50.0
鹵
5.0
INPUT RESTRICTIONS
RECOMMENDED
ABSOLUTE
Max Freq
Min P.W.
Max Freq
Min P.W.
27.8 MHz
18.0 ns
166.7 MHz
3.00 ns
23.8 MHz
21.0 ns
153.8 MHz
3.25 ns
20.8 MHz
24.0 ns
142.8 MHz
3.50 ns
18.5 MHz
27.0 ns
133.3 MHz
3.75 ns
16.7 MHz
30.0 ns
125.0 MHz
4.00 ns
13.9 MHz
36.0 ns
111.1 MHz
4.50 ns
11.9 MHz
42.0 ns
100.0 MHz
5.00 ns
10.4 MHz
48.0 ns
83.3 MHz
6.00 ns
8.33 MHz
60.0 ns
62.5 MHz
8.00 ns
6.67 MHz
75.0 ns
50.0 MHz
10.00 ns
5.56 MHz
90.0 ns
41.7 MHz
12.00 ns
4.42 MHz
113 ns
33.3 MHz
15.00 ns
3.33 MHz
150 ns
25.0 MHz
20.00 ns
2.66 MHz
188 ns
20.0 MHz
25.00 ns
2.22 MHz
225 ns
16.7 MHz
30.00 ns
1.67 MHz
300 ns
12.5 MHz
40.00 ns
1.33 MHz
375 ns
10.0 MHz
50.00 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns
鹵
1.5ns
NOTE: Any dash number between 1 and 50 not shown is also available as standard product
餂?002
Data Delay Devices
Doc #01015
11/8/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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