鈥?/div>
data
3
廬
delay
devices,
inc.
PACKAGES
IN
N/C
N/C
O2
N/C
O4
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VDD
N/C
O1
N/C
O3
N/C
O5
IN
1 8
VDD
All-silicon, low-power CMOS
VDD
IN
1
8
O2
2 7
O1
technology
O4
3 6
O3
O1
O2
2
7
GND
4 5
O5
TTL/CMOS compatible
O3
O4
3
6
inputs and outputs
3D7105Z
O5
GND
4
5
SOIC
Vapor phase, IR and wave
(150 Mil)
solderable
3D7105M DIP
Auto-insertable (DIP pkg.)
3D7105H Gull-Wing
(300 Mil)
Low ground bounce noise
Leading- and trailing-edge accuracy
IN
1
16
VDD
Delay range:
.75 through 80ns
N/C
2
15
N/C
Delay tolerance:
5% or 1ns
N/C
3
14
N/C
O2
4
13
O1
Temperature stability:
鹵3%
typical (0C-70C)
N/C
5
12
N/C
O4
6
11
O3
Vdd stability:
鹵1%
typical (4.75V-5.25V)
N/C
7
10
N/C
GND
8
9
O5
Minimum input pulse width:
30% of total delay
14-pin DIP and 16-pin SOIC available as drop-in
3D7105S SOIC
replacements for hybrid delay lines
(300 Mil)
3D7105 DIP
3D7105G Gull-Wing
3D7105K Unused pins
removed
(300 Mil)
FUNCTIONAL DESCRIPTION
The 3D7105 5-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 0.75ns through 8.0ns. The
input is reproduced at the outputs without inversion, shifted in time as per
the user-specified dash number. The 3D7105 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
VCC
GND
N/C
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+5 Volts
Ground
No Connection
The all-CMOS 3D7105 integrated circuit has been designed as a reliable,
economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP
and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DIP-8
3D7105M
3D7105H
SOIC-8
3D7105Z
DIP-14
3D7105
3D7105G
3D7105K
SOIC-16
3D7105S
TOLERANCES
TOTAL
DELAY (ns)
TAP-TAP
DELAY
(ns)
Max
Operating
Frequency
INPUT RESTRICTIONS
Absolute
Max
Oper. Freq.
Min
Operating
Pulse Width
Absolute
Min
Oper. P.W.
-.75
-.75
-.75
-.75
41.7 MHz
3.0
鹵
1.0*
0.75
鹵
0.4
-1
-1
-1
-1
37.0 MHz
4.0
鹵
1.0*
1.0
鹵
0.5
-1.5
-1.5
-1.5
-1.5
30.3 MHz
6.0
鹵
1.0*
1.5
鹵
0.7
-2
-2
-2
-2
25.6 MHz
8.0
鹵
1.0*
2.0
鹵
0.8
-2.5
-2.5
-2.5
-2.5
22.2 MHz
10.0
鹵
1.0*
2.5
鹵
1.0
-4
-4
-4
-4
15.9 MHz
16.0
鹵
1.0*
4.0
鹵
1.3
-5
-5
-5
-5
13.3 MHz
25.0
鹵
1.3
5.0
鹵
1.5
-8
-8
-8
-8
9.52 MHz
40.0
鹵
2.0
8.0
鹵
1.5
* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns
鹵
1.0ns
NOTE: Any dash number between .75 and 8 not shown is also available.
166.7 MHz
166.7 MHz
166.7 MHz
166.7 MHz
133.3 MHz
83.3 MHz
66.7 MHz
41.7 MHz
12.0 ns
13.5 ns
16.5 ns
19.5 ns
22.5 ns
31.5 ns
37.5 ns
52.5 ns
3.00 ns
3.00 ns
3.00 ns
3.00 ns
3.75 ns
6.00 ns
7.50 ns
12.0 ns
漏
1996 Data Delay Devices
Doc #96006
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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