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All-silicon, low-power CMOS technology*
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP package)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
8 through 500ns
Delay tolerance:
5% or 2ns
Temperature stability:
鹵3%
typical (0C-70C)
Vdd stability:
鹵2%
typical (4.75V-5.25V)
Minimum input pulse width:
20% of total
delay
IN
N/C
O2
O4
O6
O8
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
data
3
廬
delay
devices,
inc.
PACKAGES
VDD
O1
O3
O5
O7
O9
O10
IN
N/C
N/C
O2
O4
O6
O8
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
N/C
O1
O3
O5
O7
O9
O10
3D7010 DIP
3D7010G Gull-Wing
(300 Mil)
3D7010S
SOIC
(300 Mil)
(For mechanical data, see Case Dimensions document)
FUNCTIONAL DESCRIPTION
The 3D7010 10-Tap Delay Line product family consists of fixed-delay
CMOS integrated circuits. Each package contains a single delay line,
tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap
(incremental) delay values can range from 8ns through 50ns. The input
is reproduced at the outputs without inversion, shifted in time as per the
user-specified dash number. The 3D7010 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features both
rising- and falling-edge accuracy.
The all-CMOS 3D7010 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
VCC
GND
Delay Line Input
Tap 1 Output (10%)
Tap 2 Output (20%)
Tap 3 Output (30%)
Tap 4 Output (40%)
Tap 5 Output (50%)
Tap 6 Output (60%)
Tap 7 Output (70%)
Tap 8 Output (80%)
Tap 9 Output (90%)
Tap 10 Output (100%)
+5 Volts
Ground
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER
DIP-14
SOIC-16
3D7010
3D7010S
3D7010G
-80
-80
-90
-90
-100
-100
-150
-150
-200
-200
-250
-250
-300
-300
-400
-400
-500
-500
NOTE:
TOLERANCES
TOTAL
TAP-TO-TAP
DELAY
DELAY
(ns)
(ns)
80
鹵
4.0
8.0
鹵
1.5
90
鹵
4.5
9.0
鹵
1.7
100
鹵
5.0
10.0
鹵
2.0
150
鹵
7.5
15.0
鹵
2.0
200
鹵
10.0
20.0
鹵
2.5
250
鹵
12.5
25.0
鹵
2.5
300
鹵
15.0
30.0
鹵
3.0
400
鹵
20.0
40.0
鹵
4.0
500
鹵
25.0
50.0
鹵
5.0
Max Operating
Frequency
4.17 MHz
3.70 MHz
3.33 MHz
2.22 MHz
1.67 MHz
1.33 MHz
1.11 MHz
0.83 MHz
0.67 MHz
INPUT RESTRICTIONS
Absolute Max
Min Operating
Oper. Freq.
Pulse Width
31.2 MHz
27.8 MHz
25.0 MHz
16.7 MHz
12.5 MHz
10.0 MHz
8.33 MHz
6.25 MHz
5.00 MHz
120.0 ns
135.0 ns
150.0 ns
225.0 ns
300.0 ns
375.0 ns
450.0 ns
600.0 ns
750.0 ns
Absolute Min
Oper. P.W.
16.0 ns
18.0 ns
20.0 ns
30.0 ns
40.0 ns
50.0 ns
60.0 ns
80.0 ns
100.0 ns
Any dash number between 80 and 500 not shown is also available.
漏
1996 Data Delay Devices
*PATENTED
Doc #96004
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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