鈥?/div>
All-silicon, low-power 3.3V CMOS technology
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Delay range:
1.5ns through 300ns
Total delay tolerance:
2% or 0.5ns (3.3V, 25C)
Temperature stability:
鹵1%
typical (0C-70C)
Vdd stability:
鹵1%
typical (3.0V-3.6V)
Static Idd:
1.3ma typical
Minimum input pulse width:
25% of total delay
IN
O2
O4
GND
1
2
3
4
8
7
6
5
data
3
廬
delay
devices,
inc.
PACKAGES
VDD
O1
O3
O5
IN
O2
O4
GND
1
2
3
4
8
7
6
5
VDD
O1
O3
O5
3D3215Z-xx
SOIC (150 Mil)
3D3215M-xx
DIP (300 Mil)
For mechanical dimensions, click
here
.
For package marking details, click
here
.
FUNCTIONAL DESCRIPTION
The 3D3215 5-Tap Delay Line product family consists of fixed-delay
3.3V CMOS integrated circuits. Each package contains a single delay
line, tapped and buffered at 5 points spaced uniformly in time. Tap-to-
tap (incremental) delay values can range from 1.5ns through 60ns. The
input is reproduced at the outputs without inversion, shifted in time as
per the user-specified dash number. The 3D3215 is 3.3V CMOS-
compatible and features both rising- and falling-edge accuracy.
PIN DESCRIPTIONS
IN
O1
O2
O3
O4
O5
VDD
GND
N/C
Delay Line Input
Tap 1 Output (20%)
Tap 2 Output (40%)
Tap 3 Output (60%)
Tap 4 Output (80%)
Tap 5 Output (100%)
+3.3 Volts
Ground
No Connection
The all-CMOS 3D3215 integrated circuit has been designed as a
reliable, economic alternative to hybrid fixed delay lines. It is offered in a
standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
DASH #
3D3215Z-xx
3D3215M-xx
-1.5
-2
-2.5
-3
-4
-5
-6
-8
-10
-12
-15
-20
-25
-30
-40
-50
-60
DELAY SPECIFICATIONS
TOTAL
TAP-TAP
DELAY (ns)
DELAY (ns)
6.0
鹵
0.5*
1.5
鹵
0.7
8.0
鹵
0.5*
2.0
鹵
0.8
10.0
鹵
0.5*
2.5
鹵
1.0
12.0
鹵
0.5*
3.0
鹵
1.3
16.0
鹵
0.5*
4.0
鹵
1.3
20.0
鹵
0.5*
5.0
鹵
1.4
24.0
鹵
0.5*
6.0
鹵
1.4
40.0
鹵
0.8
8.0
鹵
1.4
50.0
鹵
1.0
10.0
鹵
1.5
60.0
鹵
1.2
12.0
鹵
1.5
75.0
鹵
1.5
15.0
鹵
1.5
100
鹵
2.0
20.0
鹵
2.0
125
鹵
2.5
25.0
鹵
2.5
150
鹵
3.0
30.0
鹵
3.0
200
鹵
4.0
40.0
鹵
4.0
250
鹵
5.0
50.0
鹵
5.0
300
鹵
6.0
60.0
鹵
6.0
INPUT RESTRICTIONS
RECOMMENDED
ABSOLUTE
Max Freq
Min P.W.
Max Freq
Min P.W.
23.8 MHz
21.0 ns
83.3 MHz
6.00 ns
20.8 MHz
24.0 ns
83.3 MHz
6.00 ns
18.5 MHz
27.0 ns
66.7 MHz
7.50 ns
16.7 MHz
30.0 ns
55.6 MHz
9.00 ns
13.9 MHz
36.0 ns
50.0 MHz
10.00 ns
11.9 MHz
42.0 ns
40.0 MHz
12.50 ns
10.4 MHz
48.0 ns
55.6 MHz
9.00 ns
8.33 MHz
60.0 ns
41.7 MHz
12.00 ns
6.67 MHz
75.0 ns
40.0 MHz
12.50 ns
5.56 MHz
90.0 ns
33.3 MHz
15.00 ns
4.42 MHz
113 ns
26.7 MHz
18.75 ns
3.33 MHz
150 ns
20.0 MHz
25.00 ns
2.66 MHz
188 ns
16.0 MHz
31.25 ns
2.22 MHz
225 ns
13.3 MHz
37.50 ns
1.67 MHz
300 ns
10.0 MHz
50.00 ns
1.33 MHz
375 ns
8.0 MHz
62.50 ns
1.11 MHz
450 ns
6.7 MHz
75.00 ns
* Total delay referenced to Tap1 output; Input-to-Tap1 = 7.5ns
鹵
1.5ns
NOTE: Any dash number between 1.5 and 60 not shown is also available as standard
漏
2001 Data Delay Devices
Doc #01014
12/3/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
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