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39K50 Datasheet

  • 39K50

  • CPLDs at FPGA DensitiesTM

  • 86頁

  • CYPRESS

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Delta39K鈩?ISR鈩?/div>
CPLD Family
CPLDs at FPGA Densities鈩?/div>
Features
鈥?High density
鈥?30K to 200K usable gates
鈥?512 to 3072 macrocells
鈥?136 to 428 maximum I/O pins
鈥?Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
Embedded memory
鈥?80K to 480K bits embedded SRAM
鈥?16K to 96K bits of (dual-port) channel memory
High speed 鈥?233-MHz in-system operation
AnyVolt鈩?interface
鈥?3.3V, 2.5V,1.8V, and 1.5V I/O capability
Low-power operation
鈥?0.18-mm six-layer metal SRAM-based logic process
鈥?Full-CMOS implementation of product term array
鈥?Standby current as low as 5mA
鈥?Simple timing model
鈥?No penalty for using full 16 product terms/macrocell
鈥?No delay for single product term steering or sharing
鈥?Flexible clocking
鈥?Spread Aware鈩?PLL drives all four clock networks
鈥?Allows 0.6% spread spectrum input clocks
鈥?Several multiply, divide and phase shift options
鈥?Four synchronous clock networks per device
鈥?Locally generated product term clock
鈥?Clock polarity control at each register
鈥?Carry-chain logic for fast and efficient arithmetic opera-
tions
鈥?Multiple I/O standards supported
鈥?LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
鈥?Compatible with NOBL鈩? ZBT鈩? and QDR鈩?SRAMs
鈥?Programmable slew rate control on each I/O pin
鈥?User-programmable Bus Hold capability on each I/O pin
鈥?Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
鈥?CompactPCI hot swap ready
鈥?Multiple package/pinout offering across all densities
鈥?208 to 676 pins in PQFP, BGA, and FBGA packages
鈥?Simplifies design migration across density
鈥?Self-Boot鈩?solution in BGA and FBGA packages
鈥?In-System Reprogrammable鈩?(ISR鈩?
鈥?JTAG-compliant on-board programming
鈥?Design changes do not cause pinout changes
鈥?IEEE1149.1 JTAG boundary scan
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Development Software
鈥?/div>
Warp
廬
鈥?IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
鈥?Active-HDL FSM graphical finite state machine editor
鈥?Active-HDL SIM post-synthesis timing simulator
鈥?Architecture Explorer for detailed design analysis
鈥?Static Timing Analyzer for critical path analysis
鈥?Available on Windows
錚?/div>
95/98/2000/XP鈩?and
Windows NT鈩?for $99
鈥?Supports all Cypress programmable logic products
Delta39K鈩?ISR CPLD Family Members
Typical
Gates
[1]
16K 鈥?48K
23K 鈥?72K
46K 鈥?144K
77K 鈥?241K
92K 鈥?288K
Cluster
memory
(Kbits)
64
96
192
320
384
Channel
memory
(Kbits)
16
24
48
80
96
Maximum
I/O Pins
174
218
302
386
428
f
MAX2
(MHz)
233
233
222
181
181
Speed-t
PD
Pin-to-Pin
(ns)
7.2
7.2
7.5
8.5
8.5
Standby I
CC
[2]
T
A
= 25擄C
3.3/2.5V
5 mA
5 mA
10 mA
20 mA
20 mA
Device
39K30
39K50
39K100
39K165
39K200
Macrocells
512
768
1536
2560
3072
Notes:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby I
CC
values are with PLL not utilized, no output load and stable inputs.
Cypress Semiconductor Corporation
Document #: 38-03039 Rev. *H
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised August 1, 2003

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    CPLDs at FPGA DensitiesTM
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