MirrorBit
TM
and MirrorFlash
TM
Status Bits and Erase Suspend Timing
Application Note
Introduction
As new microprocessors achieve faster and faster speeds, the response time of
flash memory has become increasingly important. When working with MirrorBit/
MirrorFlash devices, which are typically used with high-end microprocessors,
knowing how to address the response time limitations is even more important.
Two of the most common instances that engineers are faced with response time
issues are when checking the status of a program operation or when performing
multiple erase/suspend operations.
Checking Status Bits during Program Operations
With the addition of write buffers in MirrorBit/MirrorFlash devices, the response
time of the DQ Status Bits has changed slightly. When checking the program sta-
tus, the DQ Status Bits are not guaranteed to be valid until 4 碌s after the program
command (see Figure 1) is issued. Note that all program operations on MirrorBit/
MirrorFlash parts take more than 4 碌s to complete. In other words, the only sta-
tus information expected within the first 4 碌s would be 鈥淧rogram in Progress鈥?or
鈥淲rite to Buffer Operation Aborted鈥?
Publication Number
30613
Revision
A
Amendment
0
Issue Date
September 10, 2003