Silicon MOS FETs (Small Signal)
2SJ146
Silicon P-Channel MOS FET
For switching
2.8
鈥?.3
+0.2
unit: mm
0.65鹵0.15
s
Features
q
High-speed switching
q
Mini-type package, allowing downsizing of the sets and automatic
insertion through the tape/magazine packing.
0.65鹵0.15
1.5
鈥?.05
+0.25
0.95
2.9
鈥?.05
1
1.9鹵0.2
+0.2
0.95
3
0.4
鈥?.05
+0.1
2
s
Absolute Maximum Ratings
(Ta = 25擄C)
1.1
鈥?.1
+0.2
1.45
Parameter
Drain to Source breakdown voltage
Gate to Source voltage
Drain current
Max drain current
Allowable power dissipation
Channel temperature
Storage temperature
Symbol
V
DSS
V
GSO
I
D
I
DP
P
D
T
ch
T
stg
Ratings
鈭?0
鈭?
鈭?00
鈭?00
150
150
鈭?5
to +150
Unit
V
V
mA
mA
mW
擄C
擄C
1: Gate
2: Source
3: Drain
JEDEC: TO-236
EIAJ: SC-59
Mini Type Package (3-pin)
Marking Symbol: 4D
s
Electrical Characteristics
(Ta = 25擄C)
Parameter
Drain to Source cut-off current
Gate to Source leakage current
Drain to Source breakdown voltage
Gate threshold voltage
Forward transfer admittance
Drain to Source ON-resistance
Symbol
I
DSS
I
GSS
V
DSS
V
th
| Y
fs
|
R
DS(on)
C
oss
t
on*
t
off*
Conditions
V
DS
=
鈭?0V,
V
GS
= 0
V
GS
=
鈭?V,
V
DS
= 0
I
D
=
鈭?00碌A(chǔ),
V
GS
= 0
V
DS
=
鈭?V,
I
D
=
鈭?00碌A(chǔ)
V
DS
=
鈭?0V,
I
D
=
鈭?0mA,
f = 1kHz
V
GS
=
鈭?V,
I
D
=
鈭?0mA
V
DS
=
鈭?V,
V
GS
= 0, f = 1MHz
V
DD
=
鈭?V,
V
GS
= 0 to
鈭?V,
R
L
= 400鈩?/div>
V
DD
=
鈭?V,
V
GS
=
鈭?
to 0V, R
L
= 400鈩?/div>
鈭?0
鈭?.5
8
13.5
150
13
7
3
40
60
鈭?.5
min
typ
max
鈭?0
鈭?
Unit
碌A(chǔ)
碌A(chǔ)
V
V
mS
鈩?/div>
pF
pF
pF
ns
ns
Input capacitance (Common Source) C
iss
Output capacitance (Common Source)
Reverse transfer capacitance (Common Source) C
rss
Turn-on time
Turn-off time
*
t
on
, t
off
measurement circuit
V
out
400鈩?/div>
V
in
10%
90%
90%
10%
100碌F
V
GS
= 鈥?V
50鈩?/div>
V
DD
= 鈥?V
V
out
t
on
t
off
0 to 0.1
0.1 to 0.3
0.4鹵0.2
0.8
0.16
鈥?.06
+0.1
1
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