2N7002DW Datasheet

IC型號(hào)：
2N7002DW
PDF描述：
DUAL N-CHANNEL ENHANCEMENT MODE FIELD EFFECT TRANSISTOR
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69.81KB
PDF頁數(shù)：
3頁
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2N7002DW

DUAL N-CHANNEL ENHANCEMENT

MODE FIELD EFFECT TRANSISTOR

Features

路

Dual N-Channel MOSFET

Low On-Resistance

Low Gate Threshold Voltage

Low Input Capacitance

Fast Switching Speed

Low Input/Output Leakage

Ultra-Small Surface Mount Package

SOT-363

NEW PRODUCT

Dim

Min

0.10

1.15

2.00

0.30

1.80

戮

0.90

0.25

0.10

Max

0.30

1.35

2.20

0.40

2.20

0.10

1.00

0.40

0.25

KXX

B C

0.65 Nominal

Mechanical Data

路

Case: SOT-363, Molded Plastic

Terminals: Solderable per MIL-STD-202,

Method 208

Terminal Connections: See Diagram

Marking: K72

Weight: 0.006 grams (approx.)

All Dimensions in mm

Maximum Ratings

Drain-Source Voltage

@ T

= 25擄C unless otherwise specified

Symbol

DSS

DGR

Continuous

Pulsed

Continuous

Continuous @ 100擄C

Pulsed

GSS

qJA

, T

STG

2N7002DW

鹵20

鹵40

115

800

200

1.60

625

-55 to +150

Units

mW/擄C

K/W

擄C

Characteristic

Drain-Gate Voltage R

攏

1.0MW

Gate-Source Voltage (Note 1)

Drain Current (Note 1)

Total Power Dissipation

Derating above T

= 25擄C (Note 1)

Thermal Resistance, Junction to Ambient

Operating and Storage Temperature Range

Note: 1. Valid provided that terminals are kept at specified ambient temperature.

2. Pulse width

攏

300ms, duty cycle

攏

2%.

DS30120 Rev. 2P-1

1 of 3

2N7002DW

標(biāo)準(zhǔn)包裝
3,000
類別
分離式半導(dǎo)體產(chǎn)品
家庭
FET - 陣列
系列
-
FET 型
2 個(gè) N 溝道（雙）
FET 特點(diǎn)
邏輯電平門
漏極至源極電壓(Vdss)
60V
電流 - 連續(xù)漏極(Id) @ 25° C
115mA
開態(tài)Rds（最大）@ Id, Vgs @ 25° C
7.5 歐姆 @ 50mA，5V
Id 時(shí)的 Vgs(th)（最大）
2V @ 250µA
閘電荷(Qg) @ Vgs
-
輸入電容 (Ciss) @ Vds
50pF @ 25V
功率 - 最大
200mW
安裝類型
表面貼裝
封裝/外殼
6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝
SC-70-6
包裝
帶卷 (TR)
其它名稱
2N7002DWTR

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2N7002DW Datasheet

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