鈥?/div>
Pb鈭扚ree Package is Available*
MAXIMUM RATINGS
(Note 1) (T
J
= 25擄C unless otherwise noted)
Rating
Symbol
V
CEO
V
CB
I
C
I
B
Value
60
60
30
Collector鈭扙mitter Voltage
Collector鈭払ase Voltage
Unit
Vdc
Vdc
Adc
Adc
30 AMPERES
POWER TRANSISTOR
NPN SILICON
60 VOLTS, 200 WATTS
PD, POWER DISSIPATION (WATTS)
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦 脦 脦
脦 脦 脦 脦
脦 脦 脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦 脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦 脦 脦
脦
脦 脦 脦
脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦 脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦 脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦 脦 脦
脦 脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦 脦 脦
脦脦脦 脦 脦
脦
脦
脦 脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦 脦
脦 脦
脦脦脦 脦 脦
脦脦脦脦脦脦 脦
脦
脦 脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦脦
Collector Current 鈭?Continuous (Note 2)
Base Current
7.5
Total Device Dissipation @ T
C
= 25_C
Derate above 25_C
Operating and Storage Junction
Temperature Range
P
D
200
1.14
W
W/_C
_C
T
J
, T
stg
鈥?65 to + 200
THERMAL CHARACTERISTICS
Characteristic
Symbol
q
JC
q
CA
Max
Unit
TO鈭?04AA (TO鈭?)
CASE 1鈭?7
STYLE 1
Thermal Resistance, Junction鈭抰o鈭扖ase
Thermal Resistance, Case鈭抰o鈭扐mbient
0.875
34
_C/W
_C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Indicates JEDEC Registered Data.
2. Pulse Test: Pulse Width = 5
ms,
Duty Cycle
鈮?/div>
10%.
T
A
T
C
8.0 200
6.0 150
MARKING DIAGRAM
2N5302G
AYYWW
MEX
T
C
4.0 100
T
A
2.0
50
2N5302
G
A
YY
WW
MEX
160
180
200
= Device Code
= Pb鈭扚ree Package
= Location Code
= Year
= Work Week
= Country of Origin
0
0
0
20
40
60
80
100 120 140
TEMPERATURE (擄C)
ORDERING INFORMATION
Device
2N5302
Package
TO鈭?04
TO鈭?04
(Pb鈭扚ree)
Shipping
100 Units/Tray
100 Units/Tray
Figure 1. Power Temperature Derating Curve
*For additional information on our Pb鈭扚ree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
漏
Semiconductor Components Industries, LLC, 2006
2N5302G
1
March, 2006鈭?Rev. 2
Publication Order Number:
2N5302/D
1
2
3
4
5
