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2N5060/D Datasheet

  • 2N5060/D

  • Sensitive Gate Silicon Controlled Rectifiers

  • 8頁

  • ETC

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2N5060 Series
Sensitive Gate
Silicon Controlled Rectifiers
Reverse Blocking Thyristors
Annular PNPN devices designed for high volume consumer
applications such as relay and lamp drivers, small motor controls, gate
drivers for larger thyristors, and sensing and detection circuits.
Supplied in an inexpensive plastic TO-226AA (TO-92) package
which is readily adaptable for use in automatic insertion equipment.
鈥?/div>
Sensitive Gate Trigger Current 鈥?200
碌A(chǔ)
Maximum
鈥?/div>
Low Reverse and Forward Blocking Current 鈥?50
碌A(chǔ)
Maximum,
TC = 110擄C
鈥?/div>
Low Holding Current 鈥?5 mA Maximum
鈥?/div>
Passivated Surface for Reliability and Uniformity
鈥?/div>
Device Marking: Device Type, e.g., 2N5060, Date Code
MAXIMUM RATINGS
(TJ = 25擄C unless otherwise noted)
Rating
Peak Repetitive Off鈥揝tate Voltage(1)
(TJ = 40 to 110擄C, Sine Wave,
50 to 60 Hz, Gate Open)
2N5060
2N5061
2N5062
2N5064
Symbol
VDRM,
VRRM
30
60
100
200
IT(RMS)
IT(AV)
0.51
0.255
ITSM
10
Amps
0.8
Amp
Amp
TO鈥?2 (TO鈥?26AA)
CASE 029
STYLE 10
1
2
Value
Unit
Volts
Preferred Device
http://onsemi.com
SCRs
0.8 AMPERES RMS
30 thru 200 VOLTS
G
A
K
*
On-State Current RMS
(180擄 Conduction Angles; TC = 80擄C)
*Average On-State Current
(180擄 Conduction Angles)
(TC = 67擄C)
(TC = 102擄C)
*Peak Non-repetitive Surge Current,
TA = 25擄C
(1/2 cycle, Sine Wave, 60 Hz)
Circuit Fusing Considerations (t = 8.3 ms)
*Forward Peak Gate Power
(Pulse Width
1.0
碌sec;
TA = 25擄C)
3
PIN ASSIGNMENT
1
I2t
PGM
PG(AV)
IGM
VRGM
TJ
Tstg
0.4
0.1
0.01
1.0
5.0
鈥?0 to
+110
鈥?0 to
+150
A2s
Watt
Watt
2
3
Cathode
Gate
Anode
v
v
v
*Forward Average Gate Power
(TA = 25擄C, t = 8.3 ms)
*Forward Peak Gate Current
(Pulse Width
1.0
碌sec;
TA = 25擄C)
*Reverse Peak Gate Voltage
(Pulse Width
1.0
碌sec;
TA = 25擄C)
*Operating Junction Temperature Range
*Storage Temperature Range
*Indicates JEDEC Registered Data.
ORDERING INFORMATION
Amp
Volts
Preferred
devices are recommended choices for future use
and best overall value.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
擄C
擄C
(1) VDRM and VRRM for all types can be applied on a continuous basis. Ratings
apply for zero or negative gate voltage; however, positive gate voltage shall
not be applied concurrent with negative potential on the anode. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.
漏
Semiconductor Components Industries, LLC, 2000
1
May, 2000 鈥?Rev. 4
Publication Order Number:
2N5060/D

2N5060/D相關(guān)型號PDF文件下載

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    Type 2N5003 Geometry 9702 Polarity PNP
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    Type 2N5003 Geometry 9702 Polarity PNP
    SEMICOA [S...
  • 英文版
    Type 2N5004 Geometry 9202 Polarity NPN
    SEMICOA
  • 英文版
    Chip Type 2C5004 Geometry 9202 Polarity NPN
    SEMICOA [S...
  • 英文版
    Type 2N5004 Geometry 9202 Polarity NPN
    SEMICOA [S...
  • 英文版
    Type 2N5005 Geometry 9702 Polarity PNP
    SEMICOA
  • 英文版
    Chip Type 2C5153 Geometry 9221 Polarity NPN
    SEMICOA [S...
  • 英文版
    Type 2N5005 Geometry 9702 Polarity PNP
    SEMICOA [S...

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