B-18
01/99
2N5020, 2N5021
P-Channel Silicon Junction Field-Effect Transistor
樓 Analog Switches
Absolute maximum ratings at T
A
= 25隆C
Reverse Gate Source & Reverse Gate Drain Voltage
Continuous Forward Gate Current
Continuous Device Power Dissipation
Power Derating
Storage Temperature Range
鈥?50 V
50 mA
500 mW
4 mW/擄C
鈥?65擄C to + 200擄C
At 25擄C free air temperature:
Static Electrical Characteristics
Gate Source Breakdown Voltage
Gate Reverse Current
Gate Source Cutoff Voltage
Drain Saturation Current (Pulsed)
Dynamic Electrical Characteristics
Common Source
Forward Transconductance
Common Source Output Conductance
Common Source Input Capacitance
Common Source
Reverse Transfer Capacitance
g
fs
g
os
C
iss
C
rss
V
(BR)GDO
I
GSS
V
GS(OFF)
I
DSS
2N5020
Min
25
1
0.3
1.5
Max
2N5021
Min
25
1
0.5
鈥?
2.5
鈥?3.5
Max
Unit
V
nA
V
mA
Process PJ32
Test Conditions
I
G
= 1碌A(chǔ), V
DS
= 脴V
V
GS
= 15V, V
DS
= 脴V
V
DS
= 鈥?15V, I
D
= 1 nA
V
DS
= 鈥?15V, V
GS
= 脴V
鈥?0.3 鈥?1.2
1
3.5
20
25
7
1.5
6
20
25
7
mS
碌S
pF
pF
V
DS
= 鈥?15V, V
GS
= 脴V
V
DS
= 鈥?15V, V
GS
= 脴V
V
DS
= 鈥?15V, V
GS
= 脴V
V
DS
= 鈥?15V, V
GS
= 脴V
f = 1 MHz
f = 1 MHz
TO脨18 Package
Dimensions in Inches (mm)
Surface Mount
SMP5020, SMP5021
Pin Configuration
1 Source 1, 2 Gate & Case, 3 Drain
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287
FAX
(972) 276-3375
www.interfet.com
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