B-6
01/99
2N3957, 2N3958
N-Channel Dual Silicon Junction Field-Effect Transistor
樓 Low and Medium Frequency
Differential Amplifiers
樓 High Input Impedance
Amplifiers
Absolute maximum ratings at T
A
= 25隆C
Reverse Gate Source & Reverse Gate Drain Voltage
Gate Current
Total Device Power Dissipation (each side)
@ 85擄C Case Temperature (both sides)
Power Derating (both sides)
鈥?50 V
50 mA
250 mW
500 mW
4.3 mW/擄C
At 25擄C free air temperature:
Static Electrical Characteristics
Gate Source Breakdown Voltage
Gate Reverse Current
Gate Operating Current
Gate Source Voltage
Gate Source Cutoff Voltage
Gate Source Forward Voltage
Drain Saturation Current (Pulsed)
Dynamic Electrical Characteristics
Common Source
Forward Transconductance
Common Source Output Conductance
Common Source Input Capacitance
Drain Gate Capacitance
Common Source
Reverse Transfer Capacitance
Noise Figure
Differential Gate Current
Saturation Drain Current Ratio
Differential Gate Source Voltage
Differential Gate Source
Voltage with Temperature
Transconductance Ratio
g
fs
g
os
C
iss
C
dgo
C
rss
NF
| I
G1
鈥?I
G2
|
I
DSS1
/ I
DSS2
| V
GS1
鈥?V
GS2
|
鈭哣
GS1
鈥?V
GS2
鈭員
2N3957
Min
V
(BR)GSS
I
GSS
I
G
V
GS
V
GS(OFF)
V
GS(F)
I
DSS
0.5
鈥?50
鈥?100
鈥?500
鈥?50
鈥?250
鈥?4.2
鈥?0.5
鈥?
鈥?
鈥?4.5
2
5
Max
2N3958
Min
鈥?50
鈥?100
鈥?500
鈥?50
鈥?250
鈥?4.2
鈥?0.5
鈥?
0.5
鈥?
鈥?4.5
2
5
Max
Unit
V
pA
nA
pA
nA
V
V
V
V
mA
Process NJ16
Test Conditions
I
G
= 鈥?1 碌A(chǔ), V
DS
= 脴V
V
GS
= 鈥?30V, V
DS
= 脴V
V
GS
= 鈥?30V, V
DS
= 脴V
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, I
D
= 50 碌A(chǔ)
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, I
D
= 1 nA
V
DS
= 脴, I
G
= 1 mA
V
DS
= 20V, V
GS
= 脴V
T
A
= 125擄C
T
A
= 125擄C
1000 3000 1000 3000
1000
35
4
1.5
1.2
0.5
10
0.9
1
20
6
7.5
0.9
1
0.85
0.85
1000
35
4
1.5
1.2
0.5
10
1
25
8
10
1
碌S
碌S
碌S
pF
pF
pF
dB
nA
mV
mV
mV
V
DS
= 20V, V
GS
= 脴V
V
DS
= 20V, V
GS
= 脴V
V
DS
= 20V, V
GS
= 脴V
V
DS
= 20V, V
GS
= 脴V
V
DS
= 10V, I
S
= 脴A
V
DS
= 20V, V
GS
= 脴V
V
DS
= 20V, V
GS
= 脴V
R
G
= 10 M鈩?/div>
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, V
GS
= 脴V
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, I
D
= 200 碌A(chǔ)
V
DS
= 20V, I
D
= 200 碌A(chǔ)
f = 1 kHz
f = 200 MHz
f = 1 kHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 100 Hz
T
A
= 125擄C
T
A
= 25擄C
to 鈥?55擄C
T
A
= 25擄C
to 125擄C
g
fs1
/ g
fs2
f = 1 kHz
TO脨71 Package
See Section G for Outline Dimensions
1000 N. Shiloh Road, Garland, TX 75042
(972) 487-1287
FAX
(972) 276-3375
Pin Configuration
1 Source, 2 Drain, 3 Gate, 5 Source,
6 Drain, 7 Gate
www.interfet.com
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