鈩?/div>
Family
Technical
Bulletin
EPD Systems Engineering
Synchronizing
聳聳聳
RESET
and
BOOTW
to Avoid
Misconfiguring ROM Bank 0 Width
November 15, 1993
Purpose
This bulletin replaces the technical bulletin entitled
RESET-BOOTW Synchronization,
PID No. 18011,
and its first revision,
RESET-BOOTW Correction,
PID No. 18011A. This revision includes the
Revision B Am29200 microcontroller as an affected
part, and incorporates minor, nontechnical changes
throughout.
The 29K Family microcontrollers support 8-, 16-,
and 32-bit-wide ROM banks. Configuring an 8-bit-
wide boot bank (ROM Bank 0) requires that
BOOTW
and 鈥撯€撯€撯€撯€?be tied together. Any nonzero skew
RESET
between these two signals can result in the
possibility of misconfiguring the width of ROM
Bank 0. This technical bulletin describes the cause
and probability of such a misconfiguration and
discusses possible solutions, including an example
circuit.
Affected Parts
The only nonreserved selection where
BOOTW
has a
different value before and after a reset is an 8-bit-
wide boot bank. For this option, 鈥撯€撯€撯€撯€?and
BOOTW
RESET
are tied together. Any nonzero skew between these
two signals can result in the possibility of
misconfiguring the boot bank.
The processor samples 鈥撯€撯€撯€撯€?and
BOOTW
on
RESET
approximately the rising edge of
MEMCLK
. It is
difficult to be specific because during a processor
reset, the clocks may not be established yet. In
particular,
MEMCLK
is not guaranteed externally until
after 鈥撯€撯€撯€撯€?is deasserted.
RESET
When the processor recognizes the deassertion of
鈥撯€撯€撯€撯€?(the first sample where 鈥撯€撯€撯€撯€?is High), it
RESET
RESET
compares the new and previous samples of
BOOTW
.
If a rising
MEMCLK
edge occurs during the skew
region of the 鈥撯€撯€撯€撯€?and
BOOTW
signals, a
RESET
misconfiguration may occur.
MEMCLK
*RESET
BOOTW
skew
The information in this bulletin affects the following
parts:
Device
Revision
Am29200
鈩?/div>
microcontroller
Am29205
鈩?/div>
microcontroller
Am29240
鈩?/div>
microcontroller
Am29243
鈩?/div>
microcontroller
Am29245
鈩?/div>
microcontroller
The Problem
A, B
A
A
A
A
The state of
BOOTW
before and after the deassertion
of 鈥撯€撯€撯€撯€?determines the width of ROM Bank 0.
RESET
State of
Before Reset
Again, it is difficult to know whether a
misconfiguration will actually occur because of
uncertainties in the signal-hardening logic and phase
relationships of internal processor clocks. A
misconfiguration is externally visible by an
instruction fetch stream indicative of 16- or 32-bit-
wide memory (0, 2, 4, ..., or 0, 4, 8, ...) instead of the
intended 8-bit-wide bank (0, 1, 2, ...).
In a production environment, it is impossible to
RESET
guarantee zero skew between the
BOOTW
and 鈥撯€撯€撯€撯€?/div>
pins of the processor, or account for varying
processor internal delays due to process variations.
Assuming a random distribution of 鈥撯€撯€撯€撯€?/div>
RESET
deassertions relative to
INCLK
, the probability of
BOOTW
Signal
ROM Bank 0
Width (Bits)
After Reset
0
1
0
1
0
1
1
0
16
32
8
(reserved)
PID No. 18011B
1 of 3
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