CAT28C256
32K-Bit Parallel E
2
PROM
FEATURES
s
Fast Read Access Times: 120/150ns
s
Low Power CMOS Dissipation:
s
Hardware and Software Write Protection
s
Automatic Page Write Operation:
鈥揂ctive: 25 mA Max.
鈥揝tandby: 150
碌
A Max.
s
Simple Write Operation:
鈥? to 64 Bytes in 5ms
鈥揚(yáng)age Load Timer
s
End of Write Detection:
鈥揙n-Chip Address and Data Latches
鈥揝elf-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
鈥揟oggle Bit
鈥揇ATA Polling
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
s
Commerical, Industrial and Automotive
鈥?ms Max
s
CMOS and TTL Compatible I/O
Temperature Ranges
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel E
2
PROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with auto-
clear and V
CC
power up/down write protection eliminate
additional timing and protection hardware.
DATA
Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
The CAT28C256 is manufactured using Catalyst鈥檚 ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A6鈥揂14
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
5096 FHD F02
I/O0鈥揑/O7
A0鈥揂5
ADDR. BUFFER
& LATCHES
漏 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25020-0A 2/98