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24LC21A Datasheet

  • 24LC21A

  • 1K 2.5V Dual Mode I2C™ Serial EEPROM

  • 26頁(yè)

  • Microchip    Microchip

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24LC21A
1K 2.5V Dual Mode I
2
C
鈩?/div>
Serial EEPROM
FEATURES
鈥?Single supply with operation down to 2.5V
鈥?Completely implements DDC1
鈩?/div>
/DDC2
鈩?/div>
interface for monitor identi鏗乧ation, including recov-
ery to DDC1
鈥?Pin and function compatible with 24LC21
鈥?Low power CMOS technology
- 1 mA typical active current
- 10
碌
A standby current typical at 5.5V
鈥?2-wire serial interface bus, I
2
C
鈩?/div>
compatible
鈥?100 kHz (2.5V) and 400 kHz (5V) compatibility
鈥?Self-timed write cycle (including auto-erase)
鈥?Page-write buffer for up to eight bytes
鈥?10,000,000 erase/write cycles guaranteed
鈥?Data retention > 200 years
鈥?ESD Protection > 4000V
鈥?8-pin PDIP and SOIC package
鈥?Available for extended temperature ranges
- Commercial (C):
0
擄
C to +70
擄
C
- Industrial (I):
-40
擄
C to +85
擄
C
PACKAGE TYPES
PDIP
NC
NC
NC
V
SS
SOIC
1
24LC21A
2
3
4
8
7
6
5
V
CC
VCLK
SCL
SDA
NC
NC
NC
V
SS
1
24LC21A
2
3
4
8
7
6
5
V
CC
VCLK
SCL
SDA
DESCRIPTION
The Microchip Technology Inc. 24LC21A is a 128 x 8-
bit dual-mode Electrically Erasable PROM. This device
is designed for use in applications requiring storage
and serial transmission of con鏗乬uration and control
information. Two modes of operation have been imple-
mented: Transmit-Only Mode and Bi-directional Mode.
Upon power-up, the device will be in the Transmit-Only
Mode, sending a serial bit stream of the memory array
from 00h to 7Fh, clocked by the VCLK pin. A valid high
to low transition on the SCL pin will cause the device to
enter the transition mode, and look for a valid control
byte on the I
2
C bus. If it detects a valid control byte from
the master, it will switch into Bi-directional Mode, with
byte selectable read/write capability of the memory
array using SCL. If no control byte is received, the
device will revert to the Transmit-Only Mode after it
receives 128 consecutive VCLK pulses while the SCL
pin is idle. The 24LC21A is available in a standard 8-pin
PDIP and SOIC package in both commercial and
industrial temperature ranges.
BLOCK DIAGRAM
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA
SCL
YDEC
VCLK
SENSE AMP
R/W CONTROL
V
CC
V
SS
DDC is a trademark of the Video Electronics Standards Association.
I
2
C is a trademark of Philips Corporation.
漏
1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21160B-page 1

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