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SDRAM Performance Monitors with the

脡lan鈩C520 Microcontroller

Application Note

by Daniel Mann and James Magro

This application note describes the concept, design considerations, functions, and use of the

SDRAM performance monitors with the 脡lan鈩C520 microcontroller.

OVERVIEW

The 脡lan鈩C520 microcontroller includes two non-

i n t r u s i v e A d a p t i ve D i g i t a l E l e m e n t ( A D D I E )

performance monitor resources for monitoring a variety

of SDRAM controller parameters. Features of the

performance monitors include:

s

Non-intrusive (hardware)

s

Probability resolution of 0.39%

s

Less than 4% error

s

Monitoring of the following SDRAM controller pa-

rameters:

鈥?Write buffer hits (implying merge or collapse)

鈥?Read merge hits (from the write buffer)

鈥?Write buffer full occurrence

鈥?Read buffer hits

鈥?SDRAM page and bank misses

s

Two ADDIE resources that can be configured to

concurrently monitor any two SDRAM controller

parameters

Registers

The ADDIE performance monitors are controlled by the

performance monitor control registers, as shown in

Table 1.

Refer to Appendix A, 鈥淪DRAM Performance Monitor

Registers鈥?for more information about the performance

monitor registers.

Table 1.

Register Name

Performance Monitor Control

Performance Monitor Data 0

Performance Monitor Data 1

Performance Monitor Control Registers (Memory Mapped)

MMCR Offset

Address

44h

48h

49h

Function

Selects parameter to monitor for both ADDIE 0 and

ADDIE 1.

Returns ADDIE 0 performance data.

Returns ADDIE 1 performance data.

漏 Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.

Publication#

23380

Rev:

A

Amendment/0

Issue Date:

April 2000

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